| /art/compiler/utils/arm64/ |
| managed_register_arm64_test.cc | 205 reg = Arm64ManagedRegister::FromDRegister(D31);
213 EXPECT_EQ(D31, reg.AsDRegister());
215 EXPECT_TRUE(reg.Equals(Arm64ManagedRegister::FromDRegister(D31)));
257 dreg = Arm64ManagedRegister::FromDRegister(D31);
265 EXPECT_EQ(D31, reg.AsOverlappingDRegister());
[all...] |
| /external/libavc/common/arm/ |
| ih264_weighted_bi_pred_a9q.s | 338 vqmovun.s16 d31, q6 @saturating row 3H to unsigned 8-bit
|
| /external/libhevc/common/arm/ |
| ihevc_resi_trans.s | 593 VST1.64 {d30,d31},[r2],r4 @ Row 3 of transform stage 1 F2[1] stored
[all...] |
| /external/v8/src/arm64/ |
| assembler-arm64.h | 55 R(d24) R(d25) R(d26) R(d27) R(d28) R(d29) R(d30) R(d31)
466 ALIAS_REGISTER(VRegister, fp_scratch2, d31);
[all...] |
| /art/test/083-compiler-regressions/src/ |
| Main.java | 5401 double d31 = 31; local
[all...] |
| /external/llvm/test/MC/X86/AlignedBundling/ |
| autogen-inst-offset-align-to-end.s | [all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/X86/AlignedBundling/ |
| autogen-inst-offset-align-to-end.s | [all...] |
| /external/boringssl/src/crypto/poly1305/ |
| poly1305_arm_asm.S | 985 # asm 2: vld1.8 {>r4=d30->r4=d31},[<ptr=r2,: 128]
986 vld1.8 {d30-d31},[r2,: 128]
[all...] |
| /external/elfutils/tests/ |
| run-allregs.sh | [all...] |
| run-addrcfi.sh | [all...] |
| /external/vixl/test/aarch32/ |
| test-assembler-aarch32.cc | [all...] |
| /art/compiler/optimizing/ |
| code_generator_arm_vixl.cc | [all...] |
