| /external/libvpx/config/arm-neon/vpx_dsp/arm/ |
| vpx_convolve8_horiz_filter_type1_neon.asm.S | 69 vdup.8 d31, d2[7] @coeffabs_7 = vdup_lane_u8(coeffabs,
135 vmlsl.u8 q4, d7, d31 @mul_res = vmlsl_u8(src[0_7],
153 vmlsl.u8 q5, d19, d31 @mul_res = vmlsl_u8(src[0_7],
219 vmlsl.u8 q4, d18, d31 @mul_res = vmlsl_u8(src[0_7],
243 vmlsl.u8 q10, d19, d31
266 vmlsl.u8 q5, d18, d31 @mul_res = vmlsl_u8(src[0_7],
287 vmlsl.u8 q11, d19, d31
322 vmlsl.u8 q4, d18, d31 @mul_res = vmlsl_u8(src[0_7],
396 vmlsl.u8 q4, d7, d31
|
| vpx_convolve8_horiz_filter_type2_neon.asm.S | 70 vdup.8 d31, d2[7] @coeffabs_7 = vdup_lane_u8(coeffabs,
135 vmlsl.u8 q4, d7, d31 @mul_res = vmlsl_u8(src[0_7],
153 vmlsl.u8 q5, d19, d31 @mul_res = vmlsl_u8(src[0_7],
219 vmlsl.u8 q4, d18, d31 @mul_res = vmlsl_u8(src[0_7],
243 vmlsl.u8 q10, d19, d31
266 vmlsl.u8 q5, d18, d31 @mul_res = vmlsl_u8(src[0_7],
287 vmlsl.u8 q11, d19, d31
322 vmlsl.u8 q4, d18, d31 @mul_res = vmlsl_u8(src[0_7],
396 vmlsl.u8 q4, d7, d31
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
| vorr-vbic-illegal-cases.s | 12 @ CHECK: operand must be a register in range [d0, d31]
20 @ CHECK: operand must be a register in range [d0, d31]
|
| fp-armv8.s | 66 vselge.f64 d30, d31, d23
67 @ CHECK: vselge.f64 d30, d31, d23 @ encoding: [0xa7,0xeb,0x6f,0xfe]
78 vselvs.f64 d0, d1, d31
79 @ CHECK: vselvs.f64 d0, d1, d31 @ encoding: [0x2f,0x0b,0x11,0xfe]
|
| thumb-fp-armv8.s | 69 vselge.f64 d30, d31, d23
70 @ CHECK: vselge.f64 d30, d31, d23 @ encoding: [0x6f,0xfe,0xa7,0xeb]
81 vselvs.f64 d0, d1, d31
82 @ CHECK: vselvs.f64 d0, d1, d31 @ encoding: [0x11,0xfe,0x2f,0x0b]
|
| invalid-fp-armv8.s | 72 @ V8: note: operand must be a register in range [d0, d31]
76 @ V8: note: operand must be a register in range [d0, d31]
|
| /external/llvm/test/MC/ARM/ |
| fp-armv8.s | 66 vselge.f64 d30, d31, d23
67 @ CHECK: vselge.f64 d30, d31, d23 @ encoding: [0xa7,0xeb,0x6f,0xfe]
78 vselvs.f64 d0, d1, d31
79 @ CHECK: vselvs.f64 d0, d1, d31 @ encoding: [0x2f,0x0b,0x11,0xfe]
|
| thumb-fp-armv8.s | 69 vselge.f64 d30, d31, d23
70 @ CHECK: vselge.f64 d30, d31, d23 @ encoding: [0x6f,0xfe,0xa7,0xeb]
81 vselvs.f64 d0, d1, d31
82 @ CHECK: vselvs.f64 d0, d1, d31 @ encoding: [0x11,0xfe,0x2f,0x0b]
|
| /external/libavc/common/arm/ |
| ih264_iquant_itrans_recon_dc_a9.s | 151 vld1.32 d31[0], [r1], r3 @III row Load pu1_pred buf
153 vld1.32 d31[1], [r1], r3 @IV row Load pu1_pred buffer
156 vaddw.u8 q11, q0, d31
275 vld1.32 d31, [r1], r3 @ Q12 = 0x070605....0x070605....
286 vaddw.u8 q7, q8, d31
|
| ih264_deblk_chroma_a9.s | 103 vmov.i8 d31, #2 @
106 vmlal.u8 q4, d2, d31 @
107 vmlal.u8 q5, d3, d31 @Q5,Q4 = (X2(q1U) + q0U + p1U)
113 vmlal.u8 q7, d6, d31 @
114 vmlal.u8 q14, d7, d31 @Q14,Q7 = (X2(p1U) + p0U + q1U)
186 vmov.i8 d31, #2
196 vmlal.u8 q7, d0, d31
197 vmlal.u8 q8, d1, d31 @2*p1 + (p0 + q1)
201 vmlal.u8 q9, d6, d31
202 vmlal.u8 q10, d7, d31 @2*q1 + (p1 + q0
[all...] |
| ih264_inter_pred_filters_luma_vert_a9q.s | 150 vqrshrun.s16 d31, q10, #5 @ dst[0_8] = CLIP_U8((temp4 +16) >> 5)
166 vqrshrun.s16 d31, q7, #5
180 vqrshrun.s16 d31, q8, #5
189 vqrshrun.s16 d31, q9, #5
|
| ih264_resi_trans_quant_a9.s | 119 vld1.u8 d31, [r1], r4 @load first 8 pix pred row 1
128 vsubl.u8 q0, d30, d31 @find residue row 1
200 vmlal.s16 q7, d3, d31 @Multiply and add row 4
208 vmovn.s32 d31, q12 @Narrow row 2
395 vmlal.s16 q7, d3, d31 @Multiply and add row 4
403 vmovn.s32 d31, q12 @Narrow row 2
506 vld1.s32 d31[0], [r3] @load u4_qbits
517 vdup.s32 q11, d31[0] @u4_round_factor
|
| ih264_inter_pred_luma_horz_hpel_vert_qpel_a9q.s | 255 vmlal.s16 q3, d31, d22
291 vmlal.s16 q3, d31, d22
327 vmlal.s16 q3, d31, d22
351 vmlal.s16 q3, d31, d22
485 vmlal.s16 q3, d31, d22
520 vmlal.s16 q3, d31, d22
556 vmlal.s16 q3, d31, d22
581 vmlal.s16 q3, d31, d22
717 vmlal.s16 q3, d31, d22
753 vmlal.s16 q3, d31, d2
[all...] |
| /external/libavc/encoder/arm/ |
| ih264e_evaluate_intra4x4_modes_a9q.s | 261 vbit.32 d15, d31, d26
293 vbit.32 d17, d31, d28
295 vbit.32 d16, d31, d28
515 vst1.32 {d31[0]}, [r2], r4
516 vst1.32 {d31[1]}, [r2], r4
|
| /external/libhevc/common/arm/ |
| ihevc_inter_pred_luma_horz_w16out.s | 154 vdup.8 d31,d2[7] @coeffabs_7 = vdup_lane_u8(coeffabs, 7)
265 vmlsl.u8 q4,d7,d31
327 vmlsl.u8 q4,d7,d31 @store the i iteration result which is in upper part of the register
399 vmlsl.u8 q4,d7,d31 @mul_res = vmlsl_u8(src[0_7], coeffabs_7)@
411 vmlsl.u8 q5,d19,d31 @mul_res = vmlsl_u8(src[0_7], coeffabs_7)@
476 vmlsl.u8 q4,d18,d31 @mul_res = vmlsl_u8(src[0_7], coeffabs_7)@
504 vmlsl.u8 q10,d19,d31
529 vmlsl.u8 q5,d18,d31 @mul_res = vmlsl_u8(src[0_7], coeffabs_7)@
552 vmlsl.u8 q11,d19,d31
574 vmlsl.u8 q4,d18,d31 @mul_res = vmlsl_u8(src[0_7], coeffabs_7)
[all...] |
| ihevc_itrans_recon_16x16.s | 392 vqrshrn.s32 d31,q7,#shift_stage1_idct @// r2 = (a2 + b2 + rnd) >> 7(shift_stage1_idct)
399 vst1.16 {d30,d31},[r1]!
558 vqrshrn.s32 d31,q11,#shift_stage1_idct @// r7 = (a0 - b0 + rnd) >> 7(shift_stage1_idct)
591 @d31=r11
613 vtrn.32 d30,d31
632 @ d31=r3 9- 12 values
850 vqrshrn.s32 d31,q7,#shift_stage2_idct @// r2 = (a2 + b2 + rnd) >> 7(shift_stage1_idct)
866 vst1.16 {d30,d31},[r1]!
995 vqrshrn.s32 d31,q11,#shift_stage2_idct @// r7 = (a0 - b0 + rnd) >> 7(shift_stage1_idct)
1023 @d31=r1
[all...] |
| ihevc_intra_pred_filters_luma_mode_11_to_17.s | 265 vld1.8 d31, [r14]!
269 vmull.s8 q11, d30, d31 @(col+1)*intra_pred_angle [0:7](col)
420 vld1.8 d31, [r14]!
421 vmull.s8 q6, d30, d31 @(col+1)*intra_pred_angle [0:7](col)
470 vld1.8 d31, [r14]!
510 vmull.s8 q7, d30, d31 @(col+1)*intra_pred_angle [0:7](col)
598 vld1.8 d31, [r14]
609 vmull.s8 q11, d30, d31 @(col+1)*intra_pred_angle [0:7](col)
|
| ihevc_intra_pred_luma_mode_3_to_9.s | 157 vld1.8 d31, [r14]!
161 vmull.s8 q11, d30, d31 @(col+1)*intra_pred_angle [0:7](col)
310 vld1.8 d31, [r14]!
311 vmull.s8 q6, d30, d31 @(col+1)*intra_pred_angle [0:7](col)
361 vld1.8 d31, [r14]!
401 vmull.s8 q7, d30, d31 @(col+1)*intra_pred_angle [0:7](col)
484 vld1.8 d31, [r14]
492 vmull.s8 q11, d30, d31 @(col+1)*intra_pred_angle [0:7](col)
|
| ihevc_intra_pred_chroma_mode_3_to_9.s | 151 vld1.8 d31, [r14]!
155 vmull.s8 q11, d30, d31 @(col+1)*intra_pred_angle [0:7](col)
309 vld1.8 d31, [r14]!
310 vmull.s8 q6, d30, d31 @(col+1)*intra_pred_angle [0:7](col)
366 vld1.8 d31, [r14]!
410 vmull.s8 q7, d30, d31 @(col+1)*intra_pred_angle [0:7](col)
|
| ihevc_itrans_recon_32x32.s | 506 vqrshrn.s32 d31,q7,#shift_stage1_idct @// r2 = (a2 + b2 + rnd) >> 7(shift_stage1_idct)
520 vtrn.32 d30,d31
527 @ d31 =r2 1- 4 values
845 vqrshrn.s32 d31,q7,#shift_stage1_idct @// r2 = (a2 + b2 + rnd) >> 7(shift_stage1_idct)
855 vtrn.32 d30,d31
1154 vqrshrn.s32 d31,q7,#shift_stage1_idct @// r2 = (a2 + b2 + rnd) >> 7(shift_stage1_idct)
1164 vtrn.32 d30,d31
[all...] |
| /external/vixl/test/aarch32/ |
| test-simulator-cond-dt-drt-drd-drn-drm-float-f64-a32.cc | 367 const TestLoopData kTests[] = {{{F64, d3, d31, d11},
368 "F64 d3 d31 d11",
392 {{F64, d31, d28, d30},
393 "F64 d31 d28 d30",
[all...] |
| test-simulator-cond-dt-drt-drd-drn-drm-float-f64-t32.cc | 367 const TestLoopData kTests[] = {{{F64, d3, d31, d11},
368 "F64 d3 d31 d11",
392 {{F64, d31, d28, d30},
393 "F64 d31 d28 d30",
[all...] |
| /external/libmpeg2/common/arm/ |
| ideint_cac_a9.s | 81 vld1.u8 d31, [r1], r3
186 vrhadd.u8 d1, d30, d31
|
| /external/vixl/test/aarch64/ |
| test-api-aarch64.cc | 154 VIXL_CHECK(d31.IsValid());
189 VIXL_CHECK(static_cast<CPURegister>(d31).IsValid());
226 VIXL_CHECK(AreConsecutive(d31, d0));
|
| /external/capstone/suite/MC/ARM/ |
| neon-vst-encoding.s.cs | 23 0x6d,0xe8,0x40,0xf4 = vst2.16 {d30, d31}, [r0:128]!
32 0x4f,0xb5,0x44,0xf4 = vst3.16 {d27, d29, d31}, [r4]
81 0x6f,0xb6,0xc4,0xf4 = vst3.16 {d27[1], d29[1], d31[1]}, [r4]
|
