| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| R600ISelLowering.cpp | 59 addRegisterClass(MVT::i32, &R600::R600_Reg32RegClass);
68 setOperationAction(ISD::LOAD, MVT::i32, Custom);
98 setOperationAction(ISD::STORE, MVT::i32, Custom);
102 setTruncStoreAction(MVT::i32, MVT::i8, Custom);
103 setTruncStoreAction(MVT::i32, MVT::i16, Custom);
135 setCondCodeAction(ISD::SETLE, MVT::i32, Expand);
136 setCondCodeAction(ISD::SETLT, MVT::i32, Expand);
137 setCondCodeAction(ISD::SETULE, MVT::i32, Expand);
138 setCondCodeAction(ISD::SETULT, MVT::i32, Expand);
146 setOperationAction(ISD::BR_CC, MVT::i32, Expand)
[all...] |
| AMDGPUISelLowering.cpp | 127 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
153 AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32);
194 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i32, Expand);
199 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i32, Expand);
204 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i32, Expand);
238 AddPromotedToType(ISD::STORE, MVT::f32, MVT::i32);
267 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
292 setOperationAction(ISD::Constant, MVT::i32, Legal);
301 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
347 const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 }
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/test/Bindings/OCaml/ |
| core.ml | 83 insist ("i32" = (string_of_lltype i32_type));
85 insist ("i32 42" = (string_of_llvalue c))
110 (* CHECK: const_int{{.*}}i32{{.*}}-1
135 (* CHECK: const_int_string{{.*}}i32{{.*}}-1
212 (* CHECK: const_array{{.*}}[i32 3, i32 4]
229 (* CHECK: const_structure{{.*.}}i16 1, i16 2, i32 3, i32 4
374 * CHECK: const_shufflevector = global <4 x i32> <i32 0, i32 1, i32 1, i32 0
[all...] |
| /external/mesa3d/src/amd/common/ |
| ac_nir_to_llvm.c | 169 return ctx->ac.i32;
393 LLVMConstInt(ctx->i32, rshift, false), "");
398 LLVMConstInt(ctx->i32, mask, false), "");
460 LLVMConstInt(ctx->ac.i32, 4, false), "");
468 LLVMConstInt(ctx->ac.i32, 4, false), "");
692 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.base_vertex);
693 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.start_instance);
695 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.draw_id);
703 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.vertex_id);
706 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->rel_auto_id)
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| HexagonISelLoweringHVX.cpp | 203 IntOps.push_back(DAG.getConstant(IntId, dl, MVT::i32));
281 if (ElemIdx.getValueType().getSimpleVT() != MVT::i32)
282 ElemIdx = DAG.getBitcast(MVT::i32, ElemIdx);
290 return DAG.getNode(ISD::SHL, dl, MVT::i32,
291 {ElemIdx, DAG.getConstant(L, dl, MVT::i32)});
302 if (ty(Idx) != MVT::i32)
303 Idx = DAG.getBitcast(MVT::i32, Idx);
305 SDValue Mask = DAG.getConstant(32/ElemWidth - 1, dl, MVT::i32);
306 SDValue SubIdx = DAG.getNode(ISD::AND, dl, MVT::i32, {Idx, Mask});
355 if (VecTy.getVectorElementType() != MVT::i32) {
[all...] |
| HexagonISelLowering.cpp | 178 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
285 MVT::i32, Glue);
334 Callee = DAG.getTargetGlobalAddress(GAN->getGlobal(), dl, MVT::i32);
411 MemAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, MemAddr);
552 bool IsLegalType = VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32 ||
627 SDValue Zero = DAG.getConstant(0, DL, MVT::i32);
639 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Other);
651 SDValue Zero = DAG.getConstant(0, DL, MVT::i32);
680 SDValue AC = DAG.getConstant(A, dl, MVT::i32);
681 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Other)
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
| MBlazeISelDAGToDAG.cpp | 88 // getI32Imm - Return a target constant with the specified value, of type i32.
90 return CurDAG->getTargetConstant(Imm, MVT::i32);
106 if (N->getValueType(0) == MVT::i32)
156 Disp = CurDAG->getTargetConstant(imm, MVT::i32);
209 SDValue imm = CurDAG->getTargetConstant(0, MVT::i32);
228 SDValue R20Reg = CurDAG->getRegister(MBlaze::R20, MVT::i32);
235 SDValue GPReg = CurDAG->getRegister(MBlaze::R15, MVT::i32);
240 MVT::i32, MVT::Other, Ops, 3), 0);
|
| /external/swiftshader/third_party/llvm-7.0/llvm/unittests/CodeGen/ |
| ScalableVectorMVTsTest.cpp | 47 EVT Vnx4i32 = EVT::getVectorVT(Ctx, MVT::i32, 4, /*Scalable=*/true);
52 EVT Vnx2i32 = EVT::getVectorVT(Ctx, MVT::i32, EltCnt);
77 EVT V8i32 = EVT::getVectorVT(Ctx, MVT::i32, 8);
|
| /frameworks/av/camera/ndk/impl/ |
| ACameraMetadata.cpp | 134 int64_t duration = entry.data.i32[i + STREAM_DURATION_OFFSET];
218 int32_t format = entry.data.i32[i + STREAM_FORMAT_OFFSET];
219 int32_t width = entry.data.i32[i + STREAM_WIDTH_OFFSET];
220 int32_t height = entry.data.i32[i + STREAM_HEIGHT_OFFSET];
221 int32_t isInput = entry.data.i32[i + STREAM_IS_INPUT_OFFSET];
251 int32_t format = entry.data.i32[i + STREAM_FORMAT_OFFSET];
252 int32_t width = entry.data.i32[i + STREAM_WIDTH_OFFSET];
253 int32_t height = entry.data.i32[i + STREAM_HEIGHT_OFFSET];
254 int32_t isInput = entry.data.i32[i + STREAM_IS_INPUT_OFFSET];
282 int32_t format = entry.data.i32[i + STREAM_FORMAT_OFFSET]
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 164 if (ElemTy == MVT::i32) {
508 addRegisterClass(MVT::i32, &ARM::tGPRRegClass);
510 addRegisterClass(MVT::i32, &ARM::GPRRegClass);
521 setOperationAction(ISD::BITCAST, MVT::i32, Custom);
[all...] |
| /external/mesa3d/src/gallium/drivers/radeonsi/ |
| si_shader.c | 253 LLVMConstInt(ctx->i32, rshift, 0), "");
258 LLVMConstInt(ctx->i32, mask, 0), "");
330 return LLVMConstInt(ctx->i32, stride, 0);
344 return LLVMConstInt(ctx->i32, patch_dw_stride, 0);
411 return LLVMConstInt(ctx->i32, tcs_out_vertices, 0);
423 return LLVMConstInt(ctx->i32, stride * 4, 0);
429 return LLVMConstInt(ctx->i32, stride * 4, 0);
463 LLVMValueRef index = LLVMConstInt(ctx->i32, double_index, 0);
469 LLVMValueRef i32, unsigned index)
474 return LLVMBuildAShr(ctx->ac.builder, i32,
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| AMDGPUISelLowering.cpp | 55 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
63 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
72 AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32);
113 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i32, Expand);
118 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i32, Expand);
123 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i32, Expand);
157 AddPromotedToType(ISD::STORE, MVT::f32, MVT::i32);
196 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
221 setOperationAction(ISD::Constant, MVT::i32, Legal);
230 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom)
[all...] |
| /external/clang/test/Lexer/ |
| ms-extensions.c | 7 __int32 x3 = 5i32;
|
| /external/mesa3d/src/compiler/nir/ |
| nir_search_helpers.h | 51 if (val->i32[swizzle[i]] < 0)
53 if (!__is_power_of_two(val->i32[swizzle[i]]))
81 if (val->i32[swizzle[i]] > 0)
83 if (!__is_power_of_two(abs(val->i32[swizzle[i]])))
|
| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| neon-mul-accum-encoding.s | 7 @ CHECK: vmla.i32 d16, d18, d17 @ encoding: [0xa1,0x09,0x62,0xf2]
8 vmla.i32 d16, d18, d17
15 @ CHECK: vmla.i32 q9, q8, q10 @ encoding: [0xe4,0x29,0x60,0xf2]
16 vmla.i32 q9, q8, q10
39 @ CHECK: vmls.i32 d16, d18, d17 @ encoding: [0xa1,0x09,0x62,0xf3]
40 vmls.i32 d16, d18, d17
47 @ CHECK: vmls.i32 q9, q8, q10 @ encoding: [0xe4,0x29,0x60,0xf3]
48 vmls.i32 q9, q8, q10
|
| neon-mul-encoding.s | 5 vmla.i32 d16, d18, d17
9 vmla.i32 q9, q8, q10
14 @ CHECK: vmla.i32 d16, d18, d17 @ encoding: [0xa1,0x09,0x62,0xf2]
18 @ CHECK: vmla.i32 q9, q8, q10 @ encoding: [0xe4,0x29,0x60,0xf2]
46 vmls.i32 d16, d18, d17
50 vmls.i32 q9, q8, q10
55 @ CHECK: vmls.i32 d16, d18, d17 @ encoding: [0xa1,0x09,0x62,0xf3]
59 @ CHECK: vmls.i32 q9, q8, q10 @ encoding: [0xe4,0x29,0x60,0xf3]
|
| neont2-mul-accum-encoding.s | 7 vmla.i32 d16, d18, d17
11 vmla.i32 q9, q8, q10
16 @ CHECK: vmla.i32 d16, d18, d17 @ encoding: [0x62,0xef,0xa1,0x09]
20 @ CHECK: vmla.i32 q9, q8, q10 @ encoding: [0x60,0xef,0xe4,0x29]
48 vmls.i32 d16, d18, d17
52 vmls.i32 q9, q8, q10
57 @ CHECK: vmls.i32 d16, d18, d17 @ encoding: [0x62,0xff,0xa1,0x09]
61 @ CHECK: vmls.i32 q9, q8, q10 @ encoding: [0x60,0xff,0xe4,0x29]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 118 return MVT::i32;
120 return (VT.getSizeInBits() == 32) ? MVT::i32 : MVT::i64;
306 // Mips does not have i1 type, so use i32 for
346 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
350 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
351 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
352 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
353 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
354 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
357 setOperationAction(ISD::SELECT, MVT::i32, Custom)
[all...] |
| /external/tensorflow/tensorflow/lite/kernels/ |
| neg.cc | 55 Negate(input->data.i32, num_elements, output->data.i32);
|
| topk_v2.cc | 192 const int32 k = top_k->data.i32[0];
203 TopK(row_size, num_rows, input->data.f, k, output_indexes->data.i32,
207 TopK(row_size, num_rows, input->data.uint8, k, output_indexes->data.i32,
211 TopK(row_size, num_rows, input->data.int8, k, output_indexes->data.i32,
215 TopK(row_size, num_rows, input->data.i32, k, output_indexes->data.i32,
216 output_values->data.i32);
219 TopK(row_size, num_rows, input->data.i64, k, output_indexes->data.i32,
|
| /external/tensorflow/tensorflow/lite/experimental/micro/ |
| micro_interpreter_test.cc | 37 const int32_t* input_data = input->data.i32;
41 int32_t* output_data = output->data.i32;
182 TF_LITE_MICRO_EXPECT_NE(nullptr, input->data.i32);
183 input->data.i32[0] = 21;
193 TF_LITE_MICRO_EXPECT_NE(nullptr, output->data.i32);
194 TF_LITE_MICRO_EXPECT_EQ(42, output->data.i32[0]);
|
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 103 if (ElemTy == MVT::i32) {
433 addRegisterClass(MVT::i32, &ARM::tGPRRegClass);
435 addRegisterClass(MVT::i32, &ARM::GPRRegClass);
678 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
679 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
680 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
681 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
[all...] |
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/ |
| ARMGenCallingConv.inc | 81 if (LocVT == MVT::i32) {
90 if (LocVT == MVT::i32) {
105 LocVT = MVT::i32;
123 LocVT = MVT::i32;
132 if (LocVT == MVT::i32) {
147 if (LocVT == MVT::i32) {
159 if (LocVT == MVT::i32) {
170 if (LocVT == MVT::i32) {
251 if (LocVT == MVT::i32) {
260 if (LocVT == MVT::i32) {
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/unittests/FuzzMutate/ |
| OperationsTest.cpp | 86 Constant *i32 = ConstantInt::get(Type::getInt32Ty(Ctx), 0); local
95 ConstantArray::get(ArrayType::get(i32->getType(), 2), {i32, i32});
99 ConstantPointerNull::get(PointerType::get(i32->getType(), 0));
101 auto OnlyI32 = onlyType(i32->getType());
102 EXPECT_TRUE(OnlyI32.matches({}, i32));
108 AllOf(SizeIs(Ge(1u)), Each(TypesMatch(i32))));
118 AnyType.generate({}, {i32->getType(), f16->getType(), v8i8->getType()}),
119 Each(AnyOf(TypesMatch(i32), TypesMatch(f16), TypesMatch(v8i8))))
[all...] |
| /frameworks/av/services/camera/libcameraservice/device3/ |
| DistortionMapper.cpp | 82 float arrayX = static_cast<float>(array.data.i32[0]);
83 float arrayY = static_cast<float>(array.data.i32[1]);
84 mArrayWidth = static_cast<float>(array.data.i32[2]);
85 mArrayHeight = static_cast<float>(array.data.i32[3]);
90 float activeX = static_cast<float>(array.data.i32[0]);
91 float activeY = static_cast<float>(array.data.i32[1]);
92 mActiveWidth = static_cast<float>(array.data.i32[2]);
93 mActiveHeight = static_cast<float>(array.data.i32[3]);
119 int32_t weight = e.data.i32[j + 4];
123 res = mapCorrectedToRaw(e.data.i32 + j, 2, /*clamp*/true)
[all...] |
