| /external/u-boot/board/imgtec/malta/ |
| lowlevel_init.S | 32 lw t0, 0(t0)
110 lw t1, MSC01_PBC_CS0CFG_OFS(t0)
223 lw t1, MSC01_PCI_CFG_OFS(t0)
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/RISCV/ |
| compress-rv32i.s | 36 # CHECK-ALIAS: lw s0, 124(a5)
37 # CHECK-INST: c.lw s0, 124(a5)
39 lw s0, 124(a5) label
162 # CHECK-ALIAS: lw ra, 252(sp)
165 lw ra, 252(sp) label
|
| rv32c-valid.s | 20 # CHECK-INST: c.lw a2, 0(a0)
22 c.lw a2, 0(a0)
|
| /art/runtime/interpreter/mterp/mips64/ |
| main.S | 223 lw \reg, 0(AT)
272 lw \reg, 0(AT)
273 lw AT, 4(AT)
281 lw AT, 4(AT)
403 lw v0, SHADOWFRAME_NUMBER_OF_VREGS_OFFSET(a2)
405 lw v0, SHADOWFRAME_DEX_PC_OFFSET(a2)
555 lw ra, THREAD_FLAGS_OFFSET(rSELF)
|
| /art/runtime/interpreter/mterp/mips/ |
| object.S | 13 lw a2, OFF_FP_METHOD(rFP) # a2 <- method
54 lw a3, THREAD_EXCEPTION_OFFSET(rSELF)
62 %def op_iget_quick(load="lw"):
112 lw a2, OFF_FP_METHOD(rFP) # a2 <- method
116 lw a1, THREAD_EXCEPTION_OFFSET(rSELF)
|
| other.S | 198 lw a3, THREAD_EXCEPTION_OFFSET(rSELF) # get exception obj
234 lw a0, OFF_FP_RESULT_REGISTER(rFP) # get pointer to result JType
235 lw a0, 0(a0) # a0 <- result.i
249 lw a3, OFF_FP_RESULT_REGISTER(rFP) # get pointer to result JType
|
| /external/libffi/src/mips/ |
| ffitarget.h | 148 # define REG_L lw
|
| /external/llvm/test/MC/Mips/micromips32r6/ |
| valid.s | 225 lw $3, -260($gp) # CHECK: lw $3, -260($gp) # encoding: [0xfc,0x7c,0xfe,0xfc]
226 lw $3, -256($gp) # CHECK: lw $3, -256($gp) # encoding: [0x65,0xc0]
227 lw $3, 32($gp) # CHECK: lw $3, 32($gp) # encoding: [0x65,0x88]
228 lw $3, 252($gp) # CHECK: lw $3, 252($gp) # encoding: [0x65,0xbf]
229 lw $3, 256($gp) # CHECK: lw $3, 256($gp) # encoding: [0xfc,0x7c,0x01,0x00
[all...] |
| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| radeon_code.h | 292 uint32_t lw; member in struct:r300_vertex_program_code::__anon33473::__anon33474
|
| /external/python/cpython2/Modules/_ctypes/libffi/src/mips/ |
| ffitarget.h | 148 # define REG_L lw
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/micromips32r6/ |
| valid.s | 273 lw $3, -260($gp) # CHECK: lw $3, -260($gp) # encoding: [0xfc,0x7c,0xfe,0xfc]
274 lw $3, -256($gp) # CHECK: lw $3, -256($gp) # encoding: [0x65,0xc0]
275 lw $3, 32($gp) # CHECK: lw $3, 32($gp) # encoding: [0x65,0x88]
276 lw $3, 252($gp) # CHECK: lw $3, 252($gp) # encoding: [0x65,0xbf]
277 lw $3, 256($gp) # CHECK: lw $3, 256($gp) # encoding: [0xfc,0x7c,0x01,0x00
[all...] |
| /art/runtime/ |
| lock_word.h | 166 static bool IsDefault(LockWord lw) {
167 return LockWord().GetValue() == lw.GetValue();
|
| monitor.cc | 157 LockWord lw(GetObject()->GetLockWord(false));
158 switch (lw.GetState()) {
160 CHECK_EQ(owner_->GetThreadId(), lw.ThinLockOwner());
161 lock_count_ = lw.ThinLockCount();
165 CHECK_EQ(hash_code_.load(std::memory_order_relaxed), static_cast<int32_t>(lw.GetHashCode()));
177 LOG(FATAL) << "Invalid monitor state " << lw.GetState();
181 LockWord fat(this, lw.GCState());
183 bool success = GetObject()->CasLockWord(lw, fat, CASMode::kWeak, std::memory_order_release);
[all...] |
| /external/v8/src/wasm/baseline/mips/ |
| liftoff-assembler-mips.h | 41 assm->lw(dst.gp(), src);
44 assm->lw(dst.low_gp(), src);
45 assm->lw(dst.high_gp(), MemOperand(base, offset + 4));
291 lw(dst, liftoff::GetInstanceOperand());
293 lw(dst, MemOperand(dst, offset));
301 lw(dst, liftoff::GetInstanceOperand());
531 lw(reg.gp(), src);
534 lw(reg.low_gp(), src);
535 lw(reg.high_gp(), liftoff::GetHalfStackSlot(2 * index + 1));
549 lw(reg, liftoff::GetHalfStackSlot(half_index))
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/ |
| macro-li.s.s | 60 # O32-N32-PIC: lw $1, %got([[LABEL]])($gp) # encoding: [A,A,0x81,0x8f]
90 # O32-N32-PIC: lw $1, %got([[LABEL]])($gp) # encoding: [A,A,0x81,0x8f]
112 # O32-N32-PIC: lw $1, %got([[LABEL]])($gp) # encoding: [A,A,0x81,0x8f]
135 # O32-N32-PIC: lw $1, %got([[LABEL]])($gp) # encoding: [A,A,0x81,0x8f]
161 # O32-N32-PIC: lw $1, %got([[LABEL]])($gp) # encoding: [A,A,0x81,0x8f]
183 # O32-N32-PIC: lw $1, %got([[LABEL]])($gp) # encoding: [A,A,0x81,0x8f]
|
| /external/u-boot/arch/mips/lib/ |
| cache_init.S | 152 lw t1, GCR_L2_CONFIG(t0)
368 lw t1, GCR_L2_CONFIG(t0)
410 lw t1, GCR_REV(t0)
|
| /art/runtime/arch/mips/ |
| asm_support_mips.S | 75 lw \temp, \disp+4(\base)
|
| /external/u-boot/arch/microblaze/cpu/ |
| start.S | 241 1: lw r12, r21, r5 /* Load u-boot data */
296 3: lw r12, r21, r0 /* Load entry */
|
| /external/u-boot/board/pb1x00/ |
| lowlevel_init.S | 41 lw t2, 0(t1)
47 lw t2, 0(t1)
|
| /external/v8/src/mips/ |
| macro-assembler-mips.cc | 131 lw(destination, MemOperand(kRootRegister, RootRegisterOffset(index)));
138 lw(destination, MemOperand(kRootRegister, RootRegisterOffset(index)));
311 lw(scratch, MemOperand(address));
939 lw(zero_reg, rs);
1053 lw(rd, rs);
[all...] |
| macro-assembler-mips.h | 371 lw(dst, MemOperand(sp, 0));
380 lw(src2, MemOperand(sp, 0 * kPointerSize));
381 lw(src1, MemOperand(sp, 1 * kPointerSize));
387 lw(src3, MemOperand(sp, 0 * kPointerSize));
388 lw(src2, MemOperand(sp, 1 * kPointerSize));
389 lw(src1, MemOperand(sp, 2 * kPointerSize));
[all...] |
| /external/v8/src/compiler/mips/ |
| code-generator-mips.cc | 479 __ lw(ra, MemOperand(fp, StandardFrameConstants::kCallerPCOffset));
480 __ lw(fp, MemOperand(fp, StandardFrameConstants::kCallerFPOffset));
493 __ lw(scratch1, MemOperand(fp, StandardFrameConstants::kContextOffset));
500 __ lw(caller_args_count_reg,
558 __ lw(kScratchReg, MemOperand(kJavaScriptCallCodeStartRegister, offset));
559 __ lw(kScratchReg,
678 __ lw(kScratchReg, FieldMemOperand(func, JSFunction::kContextOffset));
683 __ lw(a2, FieldMemOperand(func, JSFunction::kCodeOffset));
[all...] |
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/micromips/ |
| valid.s | 92 lw $3, 32($sp) # CHECK: lw $3, 32($sp) # encoding: [0x48,0x68] label
96 lw $3, 32($gp) # CHECK: lw $3, 32($gp) # encoding: [0x65,0x88] label
174 lw $6, 4($5) # CHECK: lw $6, 4($5) # encoding: [0xfc,0xc5,0x00,0x04] label
176 lw $6, 123($sp) # CHECK: lw $6, 123($sp) # encoding: [0xfc,0xdd,0x00,0x7b] label
[all...] |
| /external/libffi/src/tile/ |
| tile.S | 48 #define LW ld
52 #define LW lw
139 LW TMP, INCOMING_STACK_ARGS
159 LW r0, r0
165 LW REG, PTR ; \
186 LW lr, r52
192 LW RETURN_REG_ADDR, TMP
201 LW r52, TMP
311 LW lr, r1
[all...] |
| /external/python/cpython2/Modules/_ctypes/libffi/src/tile/ |
| tile.S | 48 #define LW ld
52 #define LW lw
139 LW TMP, INCOMING_STACK_ARGS
159 LW r0, r0
165 LW REG, PTR ; \
186 LW lr, r52
192 LW RETURN_REG_ADDR, TMP
201 LW r52, TMP
311 LW lr, r1
[all...] |
