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  /external/v8/src/mips/
deoptimizer-mips.cc 67 __ lw(a2, MemOperand(sp, kSavedRegistersAreaSize));
83 __ lw(a1, MemOperand(fp, CommonFrameConstants::kContextOrFrameTypeOffset));
85 __ lw(a0, MemOperand(fp, JavaScriptFrameConstants::kFunctionOffset));
103 __ lw(a1, MemOperand(v0, Deoptimizer::input_offset()));
110 __ lw(a2, MemOperand(sp, i * kPointerSize));
146 __ lw(a2, MemOperand(a1, FrameDescription::frame_size_offset()));
174 __ lw(sp, MemOperand(a0, Deoptimizer::caller_frame_top_offset()));
181 __ lw(a1, MemOperand(a0, Deoptimizer::output_count_offset()));
182 __ lw(t0, MemOperand(a0, Deoptimizer::output_offset())); // t0 is output_.
187 __ lw(a2, MemOperand(t0, 0)); // output_[ix
    [all...]
code-stubs-mips.cc 63 __ lw(s0, MemOperand(sp, offset_to_argv + kCArgsSlotsSize));
72 __ lw(t0, MemOperand(t0));
98 __ lw(t2, MemOperand(t1));
195 __ lw(t9, MemOperand(sp, kCArgsSlotsSize));
201 __ lw(t0, MemOperand(t9));
352 __ lw(s0, MemOperand(s5, kNextOffset));
353 __ lw(s1, MemOperand(s5, kLimitOffset));
354 __ lw(s2, MemOperand(s5, kLevelOffset));
388 __ lw(v0, return_value_operand);
395 __ lw(a1, MemOperand(s5, kLevelOffset))
    [all...]
codegen-mips.cc 126 __ lw(t0, MemOperand(a1));
132 __ lw(t1, MemOperand(a1, 1, loadstore_chunk)); // Maybe in delay slot.
138 __ lw(t2, MemOperand(a1, 2, loadstore_chunk));
139 __ lw(t3, MemOperand(a1, 3, loadstore_chunk));
140 __ lw(t4, MemOperand(a1, 4, loadstore_chunk));
141 __ lw(t5, MemOperand(a1, 5, loadstore_chunk));
142 __ lw(t6, MemOperand(a1, 6, loadstore_chunk));
143 __ lw(t7, MemOperand(a1, 7, loadstore_chunk));
155 __ lw(t0, MemOperand(a1, 8, loadstore_chunk));
156 __ lw(t1, MemOperand(a1, 9, loadstore_chunk))
    [all...]
  /external/capstone/suite/MC/Mips/
micromips-loadstore-instructions-EB.s.cs 6 0xfc,0xc5,0x00,0x04 = lw $6, 4($5)
micromips-loadstore-instructions.s.cs 6 0xc5,0xfc,0x04,0x00 = lw $6, 4($5)
  /external/llvm/test/MC/Mips/
mips_gprel16.s 30 // CHECK: lw ${{[0-9]+}}, 0($gp)
31 lw $1, %gp_rel(var1)($gp)
54 // CHECK: lw ${{[0-9]+}}, 4($gp)
55 lw $1, %gp_rel(var2)($gp)
nacl-mask.s 47 lw $4, 0($5)
54 lw $4, 0($sp)
55 lw $4, 0($t8)
78 # CHECK-NEXT: lw $4, 0($5)
100 # CHECK: lw $4, 0($sp)
102 # CHECK: lw $4, 0($24)
178 lw $sp, 0($2)
179 lw $sp, 123($sp)
207 # CHECK-NEXT: lw $sp, 0($2)
214 # CHECK: lw $sp, 123($sp
    [all...]
do_switch1.s 29 lw $2, 4($sp)
41 lw $1, %lo($JTI0_0)($1)
hilo-addressing.s 34 lw $5, %lo($L2-$L3)($5)
36 # CHECK-INSTR: lw $5, -8($5)
micromips-expansions.s 24 # CHECK: lw $10, %lo(symbol)($10) # encoding: [0x4a'A',0xfd'A',0x00,0x00]
39 # CHECK: lw $10, 123($10) # encoding: [0x4a,0xfd,0x7b,0x00]
53 lw $t2, symbol($a0)
56 lw $t2, 655483($a0)
sort-relocation-table.s 140 lw $2, %lo(sym1)
148 lw $2, %lo(sym1)
149 lw $2, %lo(sym1)
164 lw $2, %lo(sym1)
186 lw $2, %lo(sym1)
189 lw $2, %lo(sym3)
321 lw $2, %lo(local1)
329 lw $2, %lo(local1)
330 lw $2, %lo(local1)
345 lw $2, %lo(local1
    [all...]
  /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/
mips-register-names-invalid.s 10 lw $8, 0x10($32)
mips_gprel16.s 30 // CHECK: lw ${{[0-9]+}}, 0($gp)
31 lw $1, %gp_rel(var1)($gp)
54 // CHECK: lw ${{[0-9]+}}, 4($gp)
55 lw $1, %gp_rel(var2)($gp)
nacl-mask.s 47 lw $4, 0($5)
54 lw $4, 0($sp)
55 lw $4, 0($t8)
78 # CHECK-NEXT: lw $4, 0($5)
100 # CHECK: lw $4, 0($sp)
102 # CHECK: lw $4, 0($24)
178 lw $sp, 0($2)
179 lw $sp, 123($sp)
207 # CHECK-NEXT: lw $sp, 0($2)
214 # CHECK: lw $sp, 123($sp
    [all...]
do_switch1.s 29 lw $2, 4($sp)
41 lw $1, %lo($JTI0_0)($1)
hilo-addressing.s 34 lw $5, %lo($L2-$L3)($5)
36 # CHECK-INSTR: lw $5, -8($5)
micromips-expansions.s 24 # CHECK: lw $10, %lo(symbol)($10) # encoding: [0x4a'A',0xfd'A',0x00,0x00]
39 # CHECK: lw $10, 123($10) # encoding: [0x4a,0xfd,0x7b,0x00]
53 lw $t2, symbol($a0)
56 lw $t2, 655483($a0)
sort-relocation-table.s 140 lw $2, %lo(sym1)
148 lw $2, %lo(sym1)
149 lw $2, %lo(sym1)
164 lw $2, %lo(sym1)
186 lw $2, %lo(sym1)
189 lw $2, %lo(sym3)
321 lw $2, %lo(local1)
329 lw $2, %lo(local1)
330 lw $2, %lo(local1)
345 lw $2, %lo(local1
    [all...]
  /external/eigen/bench/btl/data/
gnuplot_common_settings.hh 5 set border 31 lt -1 lw 1.000
48 set xzeroaxis lt -2 lw 1.000
49 set x2zeroaxis lt -2 lw 1.000
50 set yzeroaxis lt -2 lw 1.000
51 set y2zeroaxis lt -2 lw 1.000
  /external/v8/src/builtins/mips/
builtins-mips.cc 48 __ lw(a2, FieldMemOperand(a1, JSFunction::kPrototypeOrInitialMapOffset));
132 __ lw(t1, MemOperand(t0));
146 __ lw(cp, MemOperand(fp, ConstructFrameConstants::kContextOffset));
148 __ lw(a1, MemOperand(fp, ConstructFrameConstants::kLengthOffset));
190 __ lw(t2, FieldMemOperand(a1, JSFunction::kSharedFunctionInfoOffset));
191 __ lw(t2, FieldMemOperand(t2, SharedFunctionInfo::kFlagsOffset));
237 __ lw(a1, MemOperand(fp, ConstructFrameConstants::kConstructorOffset));
238 __ lw(a0, MemOperand(fp, ConstructFrameConstants::kLengthOffset));
262 __ lw(t1, MemOperand(t0));
286 __ lw(cp, MemOperand(fp, ConstructFrameConstants::kContextOffset))
    [all...]
  /external/u-boot/arch/mips/mach-ath79/qca953x/
lowlevel_init.S 102 lw t1, QCA953X_RESET_REG_RESET_MODULE(t0)
107 lw t1, QCA953X_RESET_REG_RESET_MODULE(t0)
122 lw t1, QCA953X_RTC_REG_SYNC_STATUS(t0)
135 lw t1, QCA953X_PLL_CLK_CTRL_REG(t0)
152 lw t1, QCA953X_PLL_CPU_CONFIG_REG(t0)
158 lw t1, QCA953X_PLL_DDR_CONFIG_REG(t0)
164 lw t1, QCA953X_PLL_CLK_CTRL_REG(t0)
  /external/libjpeg-turbo/simd/mips/
jsimd_dspr2.S 44 lw t9, 24(sp) // t9 = num_rows
45 lw s0, 28(sp) // s0 = cinfo->num_components
56 lw t2, 0(a1) // t2 = inptr = *input_buf
98 lw t2, 0(a1) // t2 = inptr = *input_buf
166 lw t7, 48(sp) // t7 = num_rows
179 lw t6, 0(a1) // t6 = input_buf[0]
180 lw t0, 0(a2)
181 lw t1, 4(a2)
182 lw t2, 8(a2)
274 lw s1, 48(sp
    [all...]
  /bionic/libc/arch-mips/bionic/
vfork.S 46 lw $v0, REGSZ*1($v0) // v0 = v0[TLS_SLOT_THREAD_ID ie 1]
  /art/runtime/mirror/
object.cc 192 LockWord lw = current_this->GetLockWord(false); local
193 switch (lw.GetState()) {
197 LockWord hash_word = LockWord::FromHashCode(GenerateIdentityHashCode(), lw.GCState());
201 if (current_this->CasLockWord(lw, hash_word, CASMode::kStrong, std::memory_order_relaxed)) {
212 Monitor::InflateThinLocked(self, h_this, lw, GenerateIdentityHashCode());
219 Monitor* monitor = lw.FatLockMonitor();
224 return lw.GetHashCode();
227 LOG(FATAL) << "Invalid state during hashcode " << lw.GetState();
  /art/runtime/interpreter/mterp/mips/
main.S 245 lw tmp, OFF_FP_DEX_INSTRUCTIONS(rFP); \
620 lw rd, 0(AT); \
629 #define LOAD_RB_OFF(rd, rbase, off) lw rd, off(rbase)
636 lw rlo, off(rbase); \
637 lw rhi, (off+4)(rbase)
652 lw AT, (off+4)(rbase); \
670 #define STACK_LOAD(rd, off) lw rd, off(sp)
719 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF)
781 lw a0, SHADOWFRAME_NUMBER_OF_VREGS_OFFSET(a2)
784 lw a0, SHADOWFRAME_DEX_PC_OFFSET(a2) # Get starting dex_p
    [all...]

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