| /external/mesa3d/src/gallium/drivers/nouveau/nvc0/ |
| nvc0_state.c | 356 SB_IMMED_3D(so, DEPTH_WRITE_ENABLE, cso->depth.writemask);
377 SB_DATA (so, cso->stencil[0].writemask);
391 SB_DATA (so, cso->stencil[1].writemask);
[all...] |
| /external/mesa3d/src/intel/compiler/ |
| brw_disasm.c | 248 static const char *const writemask[16] = { variable
744 err |= control(file, "writemask", writemask,
790 err |= control(file, "writemask", writemask,
[all...] |
| /external/capstone/arch/X86/ |
| X86Disassembler.c | 637 return translateMaskRegister(mcInst, insn->writemask);
|
| X86DisassemblerDecoder.h | 676 /* The writemask for AVX-512 instructions which is contained in EVEX.aaa */
677 Reg writemask; member in struct:InternalInstruction
|
| /external/llvm/lib/Target/X86/Disassembler/ |
| X86DisassemblerDecoder.h | 600 // The writemask for AVX-512 instructions which is contained in EVEX.aaa
601 Reg writemask; member in struct:llvm::X86Disassembler::InternalInstruction
|
| X86Disassembler.cpp | [all...] |
| X86DisassemblerDecoder.cpp | [all...] |
| /external/mesa3d/src/gallium/drivers/r300/ |
| r300_context.c | 478 dsa.depth.writemask = 1;
|
| /external/mesa3d/src/gallium/drivers/svga/ |
| svga_state_rss.c | 94 EMIT_RS(svga, curr->rt[0].writemask, COLORWRITEENABLE);
|
| /external/mesa3d/src/gallium/drivers/vc5/ |
| vc5_emit.c | 388 vc5->zsa->base.depth.writemask;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/Disassembler/ |
| X86DisassemblerDecoder.h | 604 // The writemask for AVX-512 instructions which is contained in EVEX.aaa
605 Reg writemask; member in struct:llvm::X86Disassembler::InternalInstruction
|
| X86Disassembler.cpp | [all...] |
| X86DisassemblerDecoder.cpp | [all...] |
| /external/mesa3d/src/gallium/auxiliary/vl/ |
| vl_mpeg12_decoder.c | 865 dsa.depth.writemask = 0;
874 dsa.stencil[i].writemask = 0;
[all...] |
| vl_compositor.c | 620 dsa.depth.writemask = 0;
629 dsa.stencil[i].writemask = 0;
[all...] |
| /external/mesa3d/src/gallium/drivers/virgl/ |
| virgl_encode.c | 127 VIRGL_OBJ_DSA_S0_DEPTH_WRITEMASK(dsa_state->depth.writemask) |
140 VIRGL_OBJ_DSA_S1_STENCIL_WRITEMASK(dsa_state->stencil[i].writemask);
[all...] |
| /external/virglrenderer/tests/ |
| testvirgl_encode.c | 120 VIRGL_OBJ_DSA_S0_DEPTH_WRITEMASK(dsa_state->depth.writemask) |
133 VIRGL_OBJ_DSA_S1_STENCIL_WRITEMASK(dsa_state->stencil[i].writemask);
[all...] |
| /external/mesa3d/src/gallium/auxiliary/util/ |
| u_blitter.c | 106 void *blend[PIPE_MASK_RGBA+1][2]; /**< blend state with writemask */
234 dsa.depth.writemask = 1;
245 dsa.stencil[0].writemask = 0xff;
250 dsa.depth.writemask = 0;
[all...] |
| /external/mesa3d/src/gallium/drivers/swr/ |
| swr_state.cpp | [all...] |
| /external/mesa3d/src/gallium/drivers/r600/ |
| evergreen_state.c | 426 dsa->writemask[0] = state->stencil[0].writemask;
427 dsa->writemask[1] = state->stencil[1].writemask;
428 dsa->zwritemask = state->depth.writemask;
431 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
[all...] |
| /external/mesa3d/src/gallium/auxiliary/tgsi/ |
| tgsi_exec.c | 1051 uint writemask = inst->Dst[0].Register.WriteMask; local
1052 if (writemask == TGSI_WRITEMASK_X ||
1053 writemask == TGSI_WRITEMASK_Y ||
1054 writemask == TGSI_WRITEMASK_Z ||
1055 writemask == TGSI_WRITEMASK_W ||
1056 writemask == TGSI_WRITEMASK_NONE) {
[all...] |
| /external/mesa3d/src/mesa/state_tracker/ |
| st_cb_drawpixels.c | 625 dsa.stencil[0].writemask = ctx->Stencil.WriteMask[0] & 0xff;
630 dsa.depth.writemask = ctx->Depth.Mask;
[all...] |
| /external/virglrenderer/src/ |
| vrend_decode.c | 485 dsa_state->depth.writemask = (tmp >> 1) & 0x1;
499 dsa_state->stencil[i].writemask = (tmp >> 21) & 0xff;
[all...] |
| /external/mesa3d/src/gallium/drivers/radeonsi/ |
| si_shader.c | 1411 uint32_t writemask = reg->Register.WriteMask; local
7609 unsigned writemask = (key->ps_prolog.colors_read >> (i * 4)) & 0xf; local
[all...] |
| /external/mesa3d/src/gallium/state_trackers/nine/ |
| nine_ff.c | 623 unsigned c, writemask; local
657 tmp.WriteMask = TGSI_WRITEMASK_XYZ;
667 tmp.WriteMask = TGSI_WRITEMASK_XYZW;
671 tmp.WriteMask = TGSI_WRITEMASK_XYZ;
693 tmp.WriteMask = TGSI_WRITEMASK_XYZW;
706 writemask = TGSI_WRITEMASK_XYZW;
725 writemask = (1 << dim_output) - 1;
729 ureg_MOV(ureg, ureg_writemask(oTex, writemask), ureg_src(transformed));
[all...] |
