| /external/u-boot/arch/arm/dts/ |
| imx53-pinfunc.h | [all...] |
| imx6sl-pinfunc.h | 401 #define MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV 0x128 0x418 0x704 0x0 0x1
402 #define MX6SL_PAD_FEC_CRS_DV__SD4_DATA1 0x128 0x418 0x860 0x1 0x1
403 #define MX6SL_PAD_FEC_CRS_DV__AUD6_TXC 0x128 0x418 0x624 0x2 0x0
404 #define MX6SL_PAD_FEC_CRS_DV__ECSPI4_MISO 0x128 0x418 0x6d4 0x3 0x1
405 #define MX6SL_PAD_FEC_CRS_DV__GPT_COMPARE2 0x128 0x418 0x000 0x4 0x0
406 #define MX6SL_PAD_FEC_CRS_DV__GPIO4_IO25 0x128 0x418 0x000 0x5 0x0
407 #define MX6SL_PAD_FEC_CRS_DV__ARM_TRACE31 0x128 0x418 0x000 0x6 0x0
[all...] |
| imx6dl-pinfunc.h | 308 #define MX6QDL_PAD_EIM_A22__EIM_ADDR22 0x128 0x4f8 0x000 0x0 0x0
309 #define MX6QDL_PAD_EIM_A22__IPU1_DISP1_DATA17 0x128 0x4f8 0x000 0x1 0x0
310 #define MX6QDL_PAD_EIM_A22__IPU1_CSI1_DATA17 0x128 0x4f8 0x8a4 0x2 0x0
311 #define MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x128 0x4f8 0x000 0x5 0x0
312 #define MX6QDL_PAD_EIM_A22__SRC_BOOT_CFG22 0x128 0x4f8 0x000 0x7 0x0
313 #define MX6QDL_PAD_EIM_A22__EPDC_GDSP 0x128 0x4f8 0x000 0x8 0x0
[all...] |
| imx6q-pinfunc.h | 338 #define MX6QDL_PAD_EIM_DA5__EIM_AD05 0x128 0x43c 0x000 0x0 0x0
339 #define MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DATA04 0x128 0x43c 0x000 0x1 0x0
340 #define MX6QDL_PAD_EIM_DA5__IPU2_CSI1_DATA04 0x128 0x43c 0x000 0x2 0x0
341 #define MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x128 0x43c 0x000 0x5 0x0
342 #define MX6QDL_PAD_EIM_DA5__SRC_BOOT_CFG05 0x128 0x43c 0x000 0x7 0x0
[all...] |
| /external/u-boot/arch/arm/include/asm/arch-mx5/ |
| iomux-mx53.h | [all...] |
| /external/boringssl/src/third_party/fiat/ |
| p256_32.h | 278 uint32_t x128; local
279 fiat_p256_mulx_u32(&x127, &x128, x107, UINT32_C(0xffffffff));
294 fiat_p256_addcarryx_u32(&x137, &x138, x136, 0x0, x128);
1327 uint32_t x128; local
2600 uint32_t x128; local
[all...] |
| curve25519_32.h | 232 uint64_t x128 = (x126 + x107); local
233 uint64_t x129 = (x128 >> 26);
234 uint32_t x130 = (uint32_t)(x128 & UINT32_C(0x3ffffff));
[all...] |
| /bionic/libc/kernel/uapi/linux/ |
| input-event-codes.h | 327 #define BTN_BASE3 0x128
|
| /device/linaro/bootloader/OpenPlatformPkg/Drivers/Usb/DwUsbDxe/ |
| DwUsbDxe.h | 258 #define DIEPTXF10 0x128
|
| /external/kernel-headers/original/uapi/linux/ |
| input-event-codes.h | 373 #define BTN_BASE3 0x128
|
| /external/libunwind/src/ptrace/ |
| _UPT_reg_offset.c | 244 [UNW_HPPA_FR + 20] = 0x120, [UNW_HPPA_FR + 21] = 0x128,
|
| /external/mesa3d/src/gallium/drivers/nouveau/nv50/ |
| nv50_miptree.c | 90 tile_flags = 0x128 + ms;
|
| /external/u-boot/include/dt-bindings/input/ |
| linux-event-codes.h | 372 #define BTN_BASE3 0x128
|
| /external/u-boot/include/dt-bindings/pinctrl/ |
| pins-imx8mq.h | 244 #define MX8MQ_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x128 0x390 0x000 0x0 0x0
245 #define MX8MQ_IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x128 0x390 0x000 0x1 0x0
246 #define MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13 0x128 0x390 0x000 0x5 0x0
247 #define MX8MQ_IOMUXC_NAND_DATA07_SIM_M_HADDR9 0x128 0x390 0x000 0x7 0x0
[all...] |
| /external/vixl/test/aarch32/ |
| test-assembler-cond-sp-sp-operand-imm7-t32.cc | 171 {{al, sp, sp, 0x128}, false, al, "al sp sp 0x128", "al_sp_sp_0x128"},
|
| test-assembler-cond-rd-sp-operand-imm8-t32.cc | 169 {{al, r0, sp, 0x128}, false, al, "al r0 sp 0x128", "al_r0_sp_0x128"},
|
| /device/google/marlin/camera/mm-image-codec/qexif/ |
| qexif.h | [all...] |
| /device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/ |
| PchRegsPcu.h | [all...] |
| /external/autotest/client/bin/input/ |
| linux_input.py | 478 BTN_BASE3 = 0x128
[all...] |
| /external/openssh/ |
| pkcs11.h | 415 #define CKA_COEFFICIENT (0x128)
[all...] |
| /external/u-boot/drivers/pci/ |
| pci_tegra.c | 126 #define AFI_PEX2_CTRL 0x128
|
| /external/u-boot/drivers/net/ |
| dwc_eth_qos.c | 65 uint32_t unused_128[(0x200 - 0x128) / 4]; /* 0x128 */
[all...] |
| /external/u-boot/arch/arm/include/asm/arch-mx35/ |
| iomux-mx35.h | 406 MX35_PAD_SCK4__AUDMUX_AUD4_TXC = IOMUX_PAD(0x56c, 0x128, 0, 0x0, 0, NO_PAD_CTRL),
407 MX35_PAD_SCK4__GPIO2_30 = IOMUX_PAD(0x56c, 0x128, 5, 0x8c4, 0, NO_PAD_CTRL),
408 MX35_PAD_SCK4__ARM11P_TOP_ARM_COREASID2 = IOMUX_PAD(0x56c, 0x128, 7, 0x0, 0, NO_PAD_CTRL),
[all...] |
| /device/linaro/bootloader/OpenPlatformPkg/Chips/Hisilicon/Include/Regs/ |
| HisiPcieV1RegOffset.h | 68 #define PCIE_EEP_AER_CAP10_REG (0x128)
[all...] |
| /device/google/bonito/sdm710/kernel-headers/linux/mfd/wcd9xxx/ |
| wcd9320_registers.h | 226 #define TAIKO_A_MICB_CFILT_1_CTL (0x128)
[all...] |
