| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/ |
| armv8.4a-ldst-error.s | 39 ldapursh x3, [x24, #-257]
136 //CHECK-ERROR-NEXT: ldapursh x3, [x24, #-257]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/virt/ |
| valid.s | 12 mfhgc0 $5, $4 # CHECK: mfhgc0 $5, $4, 0 # encoding: [0x40,0x65,0x24,0x00]
13 mfhgc0 $5, $4, 7 # CHECK: mfhgc0 $5, $4, 7 # encoding: [0x40,0x65,0x24,0x07]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/RISCV/ |
| rv64m-valid.s | 14 # CHECK: encoding: [0xbb,0x53,0x24,0x03]
|
| /external/u-boot/arch/arm/include/asm/arch-tegra114/ |
| gp_padctrl.h | 69 #define SDIOCFG_DRVUP 0x24
|
| /external/u-boot/arch/arm/include/asm/arch-tegra124/ |
| gp_padctrl.h | 70 #define SDIOCFG_DRVUP 0x24
|
| /external/u-boot/arch/arm/include/asm/arch-tegra210/ |
| gp_padctrl.h | 70 #define SDIOCFG_DRVUP 0x24
|
| /external/u-boot/arch/arm/mach-at91/ |
| sdram.c | 58 writel(0xcafedede, sdram_address + 0x24);
|
| /external/u-boot/arch/sh/include/asm/ |
| cpu_sh7734.h | 42 #define IPSR9 (IPSR0 + 0x24)
|
| /external/u-boot/arch/x86/include/asm/arch-baytrail/ |
| iomap.h | 52 #define GEN_PMCON2 0x24
|
| /external/u-boot/board/armltd/integrator/ |
| integrator-sc.h | 40 #define SC_LBFCODE_OFFSET 0x24
|
| /external/u-boot/board/mpr2/ |
| lowlevel_init.S | 111 CS0WCR_A: .long BSC_BASE + 0x24
|
| /external/u-boot/board/nvidia/p2571/ |
| max77620_init.h | 24 #define MAX77620_CNFG2_L0_REG 0x24
|
| /external/u-boot/board/st/stm32mp1/ |
| board.c | 31 writel(0x00006000, GPIOG_BASE + 0x24);
|
| /external/u-boot/drivers/phy/ |
| bcm6358-usbh-phy.c | 25 #define USBH_TEST_REG 0x24
|
| /external/u-boot/drivers/phy/marvell/ |
| utmi_phy.h | 72 #define UTMI_CTRL_STATUS0_REG 0x24
|
| /external/u-boot/drivers/serial/ |
| serial_stm32.h | 22 #define RDR_OFFSET(x) (x ? 0x04 : 0x24)
|
| /external/u-boot/include/ |
| axp221.h | 40 #define AXP221_DCDC4_CTRL 0x24
|
| axp818.h | 49 #define AXP818_DCDC5_CTRL 0x24
|
| mc9sdz60.h | 55 MC9SDZ60_REG_KPD_CONTROL = 0x24,
|
| /external/u-boot/include/dt-bindings/mfd/ |
| stm32f4-rcc.h | 105 #define STM32F4_APB2_RESET(bit) (STM32F4_RCC_APB2_##bit + (0x24 * 8))
|
| /external/u-boot/include/faraday/ |
| ftsdmc020.h | 22 #define FTSDMC020_OFFSET_BANK6_BSR 0x24
|
| /external/u-boot/include/net/pfe_eth/pfe/cbus/ |
| hif.h | 22 #define HIF_RX_BDP_ADDR (HIF_BASE_ADDR + 0x24)
|
| hif_nocpy.h | 17 #define HIF_NOCPY_RX_BDP_ADDR (HIF_NOCPY_BASE_ADDR + 0x24)
|
| /external/u-boot/include/power/ |
| pfuze3000_pmic.h | 40 PFUZE3000_SW1ACONF = 0x24,
|
| stpmu1.h | 11 #define STPMU1_VREF_CTRL_REG 0x24
|
