1 //===-- PPCAsmParser.cpp - Parse PowerPC asm to MCInst instructions -------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "MCTargetDesc/PPCMCExpr.h" 11 #include "MCTargetDesc/PPCMCTargetDesc.h" 12 #include "PPCTargetStreamer.h" 13 #include "llvm/ADT/STLExtras.h" 14 #include "llvm/ADT/StringSwitch.h" 15 #include "llvm/ADT/Twine.h" 16 #include "llvm/MC/MCContext.h" 17 #include "llvm/MC/MCExpr.h" 18 #include "llvm/MC/MCInst.h" 19 #include "llvm/MC/MCInstrInfo.h" 20 #include "llvm/MC/MCParser/MCAsmLexer.h" 21 #include "llvm/MC/MCParser/MCAsmParser.h" 22 #include "llvm/MC/MCParser/MCParsedAsmOperand.h" 23 #include "llvm/MC/MCParser/MCTargetAsmParser.h" 24 #include "llvm/MC/MCRegisterInfo.h" 25 #include "llvm/MC/MCStreamer.h" 26 #include "llvm/MC/MCSubtargetInfo.h" 27 #include "llvm/MC/MCSymbolELF.h" 28 #include "llvm/Support/SourceMgr.h" 29 #include "llvm/Support/TargetRegistry.h" 30 #include "llvm/Support/raw_ostream.h" 31 32 using namespace llvm; 33 34 static const MCPhysReg RRegs[32] = { 35 PPC::R0, PPC::R1, PPC::R2, PPC::R3, 36 PPC::R4, PPC::R5, PPC::R6, PPC::R7, 37 PPC::R8, PPC::R9, PPC::R10, PPC::R11, 38 PPC::R12, PPC::R13, PPC::R14, PPC::R15, 39 PPC::R16, PPC::R17, PPC::R18, PPC::R19, 40 PPC::R20, PPC::R21, PPC::R22, PPC::R23, 41 PPC::R24, PPC::R25, PPC::R26, PPC::R27, 42 PPC::R28, PPC::R29, PPC::R30, PPC::R31 43 }; 44 static const MCPhysReg RRegsNoR0[32] = { 45 PPC::ZERO, 46 PPC::R1, PPC::R2, PPC::R3, 47 PPC::R4, PPC::R5, PPC::R6, PPC::R7, 48 PPC::R8, PPC::R9, PPC::R10, PPC::R11, 49 PPC::R12, PPC::R13, PPC::R14, PPC::R15, 50 PPC::R16, PPC::R17, PPC::R18, PPC::R19, 51 PPC::R20, PPC::R21, PPC::R22, PPC::R23, 52 PPC::R24, PPC::R25, PPC::R26, PPC::R27, 53 PPC::R28, PPC::R29, PPC::R30, PPC::R31 54 }; 55 static const MCPhysReg XRegs[32] = { 56 PPC::X0, PPC::X1, PPC::X2, PPC::X3, 57 PPC::X4, PPC::X5, PPC::X6, PPC::X7, 58 PPC::X8, PPC::X9, PPC::X10, PPC::X11, 59 PPC::X12, PPC::X13, PPC::X14, PPC::X15, 60 PPC::X16, PPC::X17, PPC::X18, PPC::X19, 61 PPC::X20, PPC::X21, PPC::X22, PPC::X23, 62 PPC::X24, PPC::X25, PPC::X26, PPC::X27, 63 PPC::X28, PPC::X29, PPC::X30, PPC::X31 64 }; 65 static const MCPhysReg XRegsNoX0[32] = { 66 PPC::ZERO8, 67 PPC::X1, PPC::X2, PPC::X3, 68 PPC::X4, PPC::X5, PPC::X6, PPC::X7, 69 PPC::X8, PPC::X9, PPC::X10, PPC::X11, 70 PPC::X12, PPC::X13, PPC::X14, PPC::X15, 71 PPC::X16, PPC::X17, PPC::X18, PPC::X19, 72 PPC::X20, PPC::X21, PPC::X22, PPC::X23, 73 PPC::X24, PPC::X25, PPC::X26, PPC::X27, 74 PPC::X28, PPC::X29, PPC::X30, PPC::X31 75 }; 76 static const MCPhysReg FRegs[32] = { 77 PPC::F0, PPC::F1, PPC::F2, PPC::F3, 78 PPC::F4, PPC::F5, PPC::F6, PPC::F7, 79 PPC::F8, PPC::F9, PPC::F10, PPC::F11, 80 PPC::F12, PPC::F13, PPC::F14, PPC::F15, 81 PPC::F16, PPC::F17, PPC::F18, PPC::F19, 82 PPC::F20, PPC::F21, PPC::F22, PPC::F23, 83 PPC::F24, PPC::F25, PPC::F26, PPC::F27, 84 PPC::F28, PPC::F29, PPC::F30, PPC::F31 85 }; 86 static const MCPhysReg VRegs[32] = { 87 PPC::V0, PPC::V1, PPC::V2, PPC::V3, 88 PPC::V4, PPC::V5, PPC::V6, PPC::V7, 89 PPC::V8, PPC::V9, PPC::V10, PPC::V11, 90 PPC::V12, PPC::V13, PPC::V14, PPC::V15, 91 PPC::V16, PPC::V17, PPC::V18, PPC::V19, 92 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 93 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 94 PPC::V28, PPC::V29, PPC::V30, PPC::V31 95 }; 96 static const MCPhysReg VSRegs[64] = { 97 PPC::VSL0, PPC::VSL1, PPC::VSL2, PPC::VSL3, 98 PPC::VSL4, PPC::VSL5, PPC::VSL6, PPC::VSL7, 99 PPC::VSL8, PPC::VSL9, PPC::VSL10, PPC::VSL11, 100 PPC::VSL12, PPC::VSL13, PPC::VSL14, PPC::VSL15, 101 PPC::VSL16, PPC::VSL17, PPC::VSL18, PPC::VSL19, 102 PPC::VSL20, PPC::VSL21, PPC::VSL22, PPC::VSL23, 103 PPC::VSL24, PPC::VSL25, PPC::VSL26, PPC::VSL27, 104 PPC::VSL28, PPC::VSL29, PPC::VSL30, PPC::VSL31, 105 106 PPC::VSH0, PPC::VSH1, PPC::VSH2, PPC::VSH3, 107 PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, 108 PPC::VSH8, PPC::VSH9, PPC::VSH10, PPC::VSH11, 109 PPC::VSH12, PPC::VSH13, PPC::VSH14, PPC::VSH15, 110 PPC::VSH16, PPC::VSH17, PPC::VSH18, PPC::VSH19, 111 PPC::VSH20, PPC::VSH21, PPC::VSH22, PPC::VSH23, 112 PPC::VSH24, PPC::VSH25, PPC::VSH26, PPC::VSH27, 113 PPC::VSH28, PPC::VSH29, PPC::VSH30, PPC::VSH31 114 }; 115 static const MCPhysReg VSFRegs[64] = { 116 PPC::F0, PPC::F1, PPC::F2, PPC::F3, 117 PPC::F4, PPC::F5, PPC::F6, PPC::F7, 118 PPC::F8, PPC::F9, PPC::F10, PPC::F11, 119 PPC::F12, PPC::F13, PPC::F14, PPC::F15, 120 PPC::F16, PPC::F17, PPC::F18, PPC::F19, 121 PPC::F20, PPC::F21, PPC::F22, PPC::F23, 122 PPC::F24, PPC::F25, PPC::F26, PPC::F27, 123 PPC::F28, PPC::F29, PPC::F30, PPC::F31, 124 125 PPC::VF0, PPC::VF1, PPC::VF2, PPC::VF3, 126 PPC::VF4, PPC::VF5, PPC::VF6, PPC::VF7, 127 PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11, 128 PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15, 129 PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19, 130 PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23, 131 PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27, 132 PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31 133 }; 134 static const MCPhysReg VSSRegs[64] = { 135 PPC::F0, PPC::F1, PPC::F2, PPC::F3, 136 PPC::F4, PPC::F5, PPC::F6, PPC::F7, 137 PPC::F8, PPC::F9, PPC::F10, PPC::F11, 138 PPC::F12, PPC::F13, PPC::F14, PPC::F15, 139 PPC::F16, PPC::F17, PPC::F18, PPC::F19, 140 PPC::F20, PPC::F21, PPC::F22, PPC::F23, 141 PPC::F24, PPC::F25, PPC::F26, PPC::F27, 142 PPC::F28, PPC::F29, PPC::F30, PPC::F31, 143 144 PPC::VF0, PPC::VF1, PPC::VF2, PPC::VF3, 145 PPC::VF4, PPC::VF5, PPC::VF6, PPC::VF7, 146 PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11, 147 PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15, 148 PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19, 149 PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23, 150 PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27, 151 PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31 152 }; 153 static unsigned QFRegs[32] = { 154 PPC::QF0, PPC::QF1, PPC::QF2, PPC::QF3, 155 PPC::QF4, PPC::QF5, PPC::QF6, PPC::QF7, 156 PPC::QF8, PPC::QF9, PPC::QF10, PPC::QF11, 157 PPC::QF12, PPC::QF13, PPC::QF14, PPC::QF15, 158 PPC::QF16, PPC::QF17, PPC::QF18, PPC::QF19, 159 PPC::QF20, PPC::QF21, PPC::QF22, PPC::QF23, 160 PPC::QF24, PPC::QF25, PPC::QF26, PPC::QF27, 161 PPC::QF28, PPC::QF29, PPC::QF30, PPC::QF31 162 }; 163 static const MCPhysReg CRBITRegs[32] = { 164 PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN, 165 PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN, 166 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, 167 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, 168 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, 169 PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN, 170 PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN, 171 PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN 172 }; 173 static const MCPhysReg CRRegs[8] = { 174 PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, 175 PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7 176 }; 177 178 // Evaluate an expression containing condition register 179 // or condition register field symbols. Returns positive 180 // value on success, or -1 on error. 181 static int64_t 182 EvaluateCRExpr(const MCExpr *E) { 183 switch (E->getKind()) { 184 case MCExpr::Target: 185 return -1; 186 187 case MCExpr::Constant: { 188 int64_t Res = cast<MCConstantExpr>(E)->getValue(); 189 return Res < 0 ? -1 : Res; 190 } 191 192 case MCExpr::SymbolRef: { 193 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E); 194 StringRef Name = SRE->getSymbol().getName(); 195 196 if (Name == "lt") return 0; 197 if (Name == "gt") return 1; 198 if (Name == "eq") return 2; 199 if (Name == "so") return 3; 200 if (Name == "un") return 3; 201 202 if (Name == "cr0") return 0; 203 if (Name == "cr1") return 1; 204 if (Name == "cr2") return 2; 205 if (Name == "cr3") return 3; 206 if (Name == "cr4") return 4; 207 if (Name == "cr5") return 5; 208 if (Name == "cr6") return 6; 209 if (Name == "cr7") return 7; 210 211 return -1; 212 } 213 214 case MCExpr::Unary: 215 return -1; 216 217 case MCExpr::Binary: { 218 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E); 219 int64_t LHSVal = EvaluateCRExpr(BE->getLHS()); 220 int64_t RHSVal = EvaluateCRExpr(BE->getRHS()); 221 int64_t Res; 222 223 if (LHSVal < 0 || RHSVal < 0) 224 return -1; 225 226 switch (BE->getOpcode()) { 227 default: return -1; 228 case MCBinaryExpr::Add: Res = LHSVal + RHSVal; break; 229 case MCBinaryExpr::Mul: Res = LHSVal * RHSVal; break; 230 } 231 232 return Res < 0 ? -1 : Res; 233 } 234 } 235 236 llvm_unreachable("Invalid expression kind!"); 237 } 238 239 namespace { 240 241 struct PPCOperand; 242 243 class PPCAsmParser : public MCTargetAsmParser { 244 const MCInstrInfo &MII; 245 bool IsPPC64; 246 bool IsDarwin; 247 248 void Warning(SMLoc L, const Twine &Msg) { getParser().Warning(L, Msg); } 249 bool Error(SMLoc L, const Twine &Msg) { return getParser().Error(L, Msg); } 250 251 bool isPPC64() const { return IsPPC64; } 252 bool isDarwin() const { return IsDarwin; } 253 254 bool MatchRegisterName(const AsmToken &Tok, 255 unsigned &RegNo, int64_t &IntVal); 256 257 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override; 258 259 const MCExpr *ExtractModifierFromExpr(const MCExpr *E, 260 PPCMCExpr::VariantKind &Variant); 261 const MCExpr *FixupVariantKind(const MCExpr *E); 262 bool ParseExpression(const MCExpr *&EVal); 263 bool ParseDarwinExpression(const MCExpr *&EVal); 264 265 bool ParseOperand(OperandVector &Operands); 266 267 bool ParseDirectiveWord(unsigned Size, SMLoc L); 268 bool ParseDirectiveTC(unsigned Size, SMLoc L); 269 bool ParseDirectiveMachine(SMLoc L); 270 bool ParseDarwinDirectiveMachine(SMLoc L); 271 bool ParseDirectiveAbiVersion(SMLoc L); 272 bool ParseDirectiveLocalEntry(SMLoc L); 273 274 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, 275 OperandVector &Operands, MCStreamer &Out, 276 uint64_t &ErrorInfo, 277 bool MatchingInlineAsm) override; 278 279 void ProcessInstruction(MCInst &Inst, const OperandVector &Ops); 280 281 /// @name Auto-generated Match Functions 282 /// { 283 284 #define GET_ASSEMBLER_HEADER 285 #include "PPCGenAsmMatcher.inc" 286 287 /// } 288 289 290 public: 291 PPCAsmParser(const MCSubtargetInfo &STI, MCAsmParser &, 292 const MCInstrInfo &MII, const MCTargetOptions &Options) 293 : MCTargetAsmParser(Options, STI), MII(MII) { 294 // Check for 64-bit vs. 32-bit pointer mode. 295 const Triple &TheTriple = STI.getTargetTriple(); 296 IsPPC64 = (TheTriple.getArch() == Triple::ppc64 || 297 TheTriple.getArch() == Triple::ppc64le); 298 IsDarwin = TheTriple.isMacOSX(); 299 // Initialize the set of available features. 300 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); 301 } 302 303 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, 304 SMLoc NameLoc, OperandVector &Operands) override; 305 306 bool ParseDirective(AsmToken DirectiveID) override; 307 308 unsigned validateTargetOperandClass(MCParsedAsmOperand &Op, 309 unsigned Kind) override; 310 311 const MCExpr *applyModifierToExpr(const MCExpr *E, 312 MCSymbolRefExpr::VariantKind, 313 MCContext &Ctx) override; 314 }; 315 316 /// PPCOperand - Instances of this class represent a parsed PowerPC machine 317 /// instruction. 318 struct PPCOperand : public MCParsedAsmOperand { 319 enum KindTy { 320 Token, 321 Immediate, 322 ContextImmediate, 323 Expression, 324 TLSRegister 325 } Kind; 326 327 SMLoc StartLoc, EndLoc; 328 bool IsPPC64; 329 330 struct TokOp { 331 const char *Data; 332 unsigned Length; 333 }; 334 335 struct ImmOp { 336 int64_t Val; 337 }; 338 339 struct ExprOp { 340 const MCExpr *Val; 341 int64_t CRVal; // Cached result of EvaluateCRExpr(Val) 342 }; 343 344 struct TLSRegOp { 345 const MCSymbolRefExpr *Sym; 346 }; 347 348 union { 349 struct TokOp Tok; 350 struct ImmOp Imm; 351 struct ExprOp Expr; 352 struct TLSRegOp TLSReg; 353 }; 354 355 PPCOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {} 356 public: 357 PPCOperand(const PPCOperand &o) : MCParsedAsmOperand() { 358 Kind = o.Kind; 359 StartLoc = o.StartLoc; 360 EndLoc = o.EndLoc; 361 IsPPC64 = o.IsPPC64; 362 switch (Kind) { 363 case Token: 364 Tok = o.Tok; 365 break; 366 case Immediate: 367 case ContextImmediate: 368 Imm = o.Imm; 369 break; 370 case Expression: 371 Expr = o.Expr; 372 break; 373 case TLSRegister: 374 TLSReg = o.TLSReg; 375 break; 376 } 377 } 378 379 // Disable use of sized deallocation due to overallocation of PPCOperand 380 // objects in CreateTokenWithStringCopy. 381 void operator delete(void *p) { ::operator delete(p); } 382 383 /// getStartLoc - Get the location of the first token of this operand. 384 SMLoc getStartLoc() const override { return StartLoc; } 385 386 /// getEndLoc - Get the location of the last token of this operand. 387 SMLoc getEndLoc() const override { return EndLoc; } 388 389 /// isPPC64 - True if this operand is for an instruction in 64-bit mode. 390 bool isPPC64() const { return IsPPC64; } 391 392 int64_t getImm() const { 393 assert(Kind == Immediate && "Invalid access!"); 394 return Imm.Val; 395 } 396 int64_t getImmS16Context() const { 397 assert((Kind == Immediate || Kind == ContextImmediate) && 398 "Invalid access!"); 399 if (Kind == Immediate) 400 return Imm.Val; 401 return static_cast<int16_t>(Imm.Val); 402 } 403 int64_t getImmU16Context() const { 404 assert((Kind == Immediate || Kind == ContextImmediate) && 405 "Invalid access!"); 406 return Imm.Val; 407 } 408 409 const MCExpr *getExpr() const { 410 assert(Kind == Expression && "Invalid access!"); 411 return Expr.Val; 412 } 413 414 int64_t getExprCRVal() const { 415 assert(Kind == Expression && "Invalid access!"); 416 return Expr.CRVal; 417 } 418 419 const MCExpr *getTLSReg() const { 420 assert(Kind == TLSRegister && "Invalid access!"); 421 return TLSReg.Sym; 422 } 423 424 unsigned getReg() const override { 425 assert(isRegNumber() && "Invalid access!"); 426 return (unsigned) Imm.Val; 427 } 428 429 unsigned getVSReg() const { 430 assert(isVSRegNumber() && "Invalid access!"); 431 return (unsigned) Imm.Val; 432 } 433 434 unsigned getCCReg() const { 435 assert(isCCRegNumber() && "Invalid access!"); 436 return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal); 437 } 438 439 unsigned getCRBit() const { 440 assert(isCRBitNumber() && "Invalid access!"); 441 return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal); 442 } 443 444 unsigned getCRBitMask() const { 445 assert(isCRBitMask() && "Invalid access!"); 446 return 7 - countTrailingZeros<uint64_t>(Imm.Val); 447 } 448 449 bool isToken() const override { return Kind == Token; } 450 bool isImm() const override { 451 return Kind == Immediate || Kind == Expression; 452 } 453 bool isU1Imm() const { return Kind == Immediate && isUInt<1>(getImm()); } 454 bool isU2Imm() const { return Kind == Immediate && isUInt<2>(getImm()); } 455 bool isU3Imm() const { return Kind == Immediate && isUInt<3>(getImm()); } 456 bool isU4Imm() const { return Kind == Immediate && isUInt<4>(getImm()); } 457 bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); } 458 bool isS5Imm() const { return Kind == Immediate && isInt<5>(getImm()); } 459 bool isU6Imm() const { return Kind == Immediate && isUInt<6>(getImm()); } 460 bool isU6ImmX2() const { return Kind == Immediate && 461 isUInt<6>(getImm()) && 462 (getImm() & 1) == 0; } 463 bool isU7Imm() const { return Kind == Immediate && isUInt<7>(getImm()); } 464 bool isU7ImmX4() const { return Kind == Immediate && 465 isUInt<7>(getImm()) && 466 (getImm() & 3) == 0; } 467 bool isU8Imm() const { return Kind == Immediate && isUInt<8>(getImm()); } 468 bool isU8ImmX8() const { return Kind == Immediate && 469 isUInt<8>(getImm()) && 470 (getImm() & 7) == 0; } 471 472 bool isU10Imm() const { return Kind == Immediate && isUInt<10>(getImm()); } 473 bool isU12Imm() const { return Kind == Immediate && isUInt<12>(getImm()); } 474 bool isU16Imm() const { 475 switch (Kind) { 476 case Expression: 477 return true; 478 case Immediate: 479 case ContextImmediate: 480 return isUInt<16>(getImmU16Context()); 481 default: 482 return false; 483 } 484 } 485 bool isS16Imm() const { 486 switch (Kind) { 487 case Expression: 488 return true; 489 case Immediate: 490 case ContextImmediate: 491 return isInt<16>(getImmS16Context()); 492 default: 493 return false; 494 } 495 } 496 bool isS16ImmX4() const { return Kind == Expression || 497 (Kind == Immediate && isInt<16>(getImm()) && 498 (getImm() & 3) == 0); } 499 bool isS16ImmX16() const { return Kind == Expression || 500 (Kind == Immediate && isInt<16>(getImm()) && 501 (getImm() & 15) == 0); } 502 bool isS17Imm() const { 503 switch (Kind) { 504 case Expression: 505 return true; 506 case Immediate: 507 case ContextImmediate: 508 return isInt<17>(getImmS16Context()); 509 default: 510 return false; 511 } 512 } 513 bool isTLSReg() const { return Kind == TLSRegister; } 514 bool isDirectBr() const { 515 if (Kind == Expression) 516 return true; 517 if (Kind != Immediate) 518 return false; 519 // Operand must be 64-bit aligned, signed 27-bit immediate. 520 if ((getImm() & 3) != 0) 521 return false; 522 if (isInt<26>(getImm())) 523 return true; 524 if (!IsPPC64) { 525 // In 32-bit mode, large 32-bit quantities wrap around. 526 if (isUInt<32>(getImm()) && isInt<26>(static_cast<int32_t>(getImm()))) 527 return true; 528 } 529 return false; 530 } 531 bool isCondBr() const { return Kind == Expression || 532 (Kind == Immediate && isInt<16>(getImm()) && 533 (getImm() & 3) == 0); } 534 bool isRegNumber() const { return Kind == Immediate && isUInt<5>(getImm()); } 535 bool isVSRegNumber() const { 536 return Kind == Immediate && isUInt<6>(getImm()); 537 } 538 bool isCCRegNumber() const { return (Kind == Expression 539 && isUInt<3>(getExprCRVal())) || 540 (Kind == Immediate 541 && isUInt<3>(getImm())); } 542 bool isCRBitNumber() const { return (Kind == Expression 543 && isUInt<5>(getExprCRVal())) || 544 (Kind == Immediate 545 && isUInt<5>(getImm())); } 546 bool isCRBitMask() const { return Kind == Immediate && isUInt<8>(getImm()) && 547 isPowerOf2_32(getImm()); } 548 bool isMem() const override { return false; } 549 bool isReg() const override { return false; } 550 551 void addRegOperands(MCInst &Inst, unsigned N) const { 552 llvm_unreachable("addRegOperands"); 553 } 554 555 void addRegGPRCOperands(MCInst &Inst, unsigned N) const { 556 assert(N == 1 && "Invalid number of operands!"); 557 Inst.addOperand(MCOperand::createReg(RRegs[getReg()])); 558 } 559 560 void addRegGPRCNoR0Operands(MCInst &Inst, unsigned N) const { 561 assert(N == 1 && "Invalid number of operands!"); 562 Inst.addOperand(MCOperand::createReg(RRegsNoR0[getReg()])); 563 } 564 565 void addRegG8RCOperands(MCInst &Inst, unsigned N) const { 566 assert(N == 1 && "Invalid number of operands!"); 567 Inst.addOperand(MCOperand::createReg(XRegs[getReg()])); 568 } 569 570 void addRegG8RCNoX0Operands(MCInst &Inst, unsigned N) const { 571 assert(N == 1 && "Invalid number of operands!"); 572 Inst.addOperand(MCOperand::createReg(XRegsNoX0[getReg()])); 573 } 574 575 void addRegGxRCOperands(MCInst &Inst, unsigned N) const { 576 if (isPPC64()) 577 addRegG8RCOperands(Inst, N); 578 else 579 addRegGPRCOperands(Inst, N); 580 } 581 582 void addRegGxRCNoR0Operands(MCInst &Inst, unsigned N) const { 583 if (isPPC64()) 584 addRegG8RCNoX0Operands(Inst, N); 585 else 586 addRegGPRCNoR0Operands(Inst, N); 587 } 588 589 void addRegF4RCOperands(MCInst &Inst, unsigned N) const { 590 assert(N == 1 && "Invalid number of operands!"); 591 Inst.addOperand(MCOperand::createReg(FRegs[getReg()])); 592 } 593 594 void addRegF8RCOperands(MCInst &Inst, unsigned N) const { 595 assert(N == 1 && "Invalid number of operands!"); 596 Inst.addOperand(MCOperand::createReg(FRegs[getReg()])); 597 } 598 599 void addRegVRRCOperands(MCInst &Inst, unsigned N) const { 600 assert(N == 1 && "Invalid number of operands!"); 601 Inst.addOperand(MCOperand::createReg(VRegs[getReg()])); 602 } 603 604 void addRegVSRCOperands(MCInst &Inst, unsigned N) const { 605 assert(N == 1 && "Invalid number of operands!"); 606 Inst.addOperand(MCOperand::createReg(VSRegs[getVSReg()])); 607 } 608 609 void addRegVSFRCOperands(MCInst &Inst, unsigned N) const { 610 assert(N == 1 && "Invalid number of operands!"); 611 Inst.addOperand(MCOperand::createReg(VSFRegs[getVSReg()])); 612 } 613 614 void addRegVSSRCOperands(MCInst &Inst, unsigned N) const { 615 assert(N == 1 && "Invalid number of operands!"); 616 Inst.addOperand(MCOperand::createReg(VSSRegs[getVSReg()])); 617 } 618 619 void addRegQFRCOperands(MCInst &Inst, unsigned N) const { 620 assert(N == 1 && "Invalid number of operands!"); 621 Inst.addOperand(MCOperand::createReg(QFRegs[getReg()])); 622 } 623 624 void addRegQSRCOperands(MCInst &Inst, unsigned N) const { 625 assert(N == 1 && "Invalid number of operands!"); 626 Inst.addOperand(MCOperand::createReg(QFRegs[getReg()])); 627 } 628 629 void addRegQBRCOperands(MCInst &Inst, unsigned N) const { 630 assert(N == 1 && "Invalid number of operands!"); 631 Inst.addOperand(MCOperand::createReg(QFRegs[getReg()])); 632 } 633 634 void addRegCRBITRCOperands(MCInst &Inst, unsigned N) const { 635 assert(N == 1 && "Invalid number of operands!"); 636 Inst.addOperand(MCOperand::createReg(CRBITRegs[getCRBit()])); 637 } 638 639 void addRegCRRCOperands(MCInst &Inst, unsigned N) const { 640 assert(N == 1 && "Invalid number of operands!"); 641 Inst.addOperand(MCOperand::createReg(CRRegs[getCCReg()])); 642 } 643 644 void addCRBitMaskOperands(MCInst &Inst, unsigned N) const { 645 assert(N == 1 && "Invalid number of operands!"); 646 Inst.addOperand(MCOperand::createReg(CRRegs[getCRBitMask()])); 647 } 648 649 void addImmOperands(MCInst &Inst, unsigned N) const { 650 assert(N == 1 && "Invalid number of operands!"); 651 if (Kind == Immediate) 652 Inst.addOperand(MCOperand::createImm(getImm())); 653 else 654 Inst.addOperand(MCOperand::createExpr(getExpr())); 655 } 656 657 void addS16ImmOperands(MCInst &Inst, unsigned N) const { 658 assert(N == 1 && "Invalid number of operands!"); 659 switch (Kind) { 660 case Immediate: 661 Inst.addOperand(MCOperand::createImm(getImm())); 662 break; 663 case ContextImmediate: 664 Inst.addOperand(MCOperand::createImm(getImmS16Context())); 665 break; 666 default: 667 Inst.addOperand(MCOperand::createExpr(getExpr())); 668 break; 669 } 670 } 671 672 void addU16ImmOperands(MCInst &Inst, unsigned N) const { 673 assert(N == 1 && "Invalid number of operands!"); 674 switch (Kind) { 675 case Immediate: 676 Inst.addOperand(MCOperand::createImm(getImm())); 677 break; 678 case ContextImmediate: 679 Inst.addOperand(MCOperand::createImm(getImmU16Context())); 680 break; 681 default: 682 Inst.addOperand(MCOperand::createExpr(getExpr())); 683 break; 684 } 685 } 686 687 void addBranchTargetOperands(MCInst &Inst, unsigned N) const { 688 assert(N == 1 && "Invalid number of operands!"); 689 if (Kind == Immediate) 690 Inst.addOperand(MCOperand::createImm(getImm() / 4)); 691 else 692 Inst.addOperand(MCOperand::createExpr(getExpr())); 693 } 694 695 void addTLSRegOperands(MCInst &Inst, unsigned N) const { 696 assert(N == 1 && "Invalid number of operands!"); 697 Inst.addOperand(MCOperand::createExpr(getTLSReg())); 698 } 699 700 StringRef getToken() const { 701 assert(Kind == Token && "Invalid access!"); 702 return StringRef(Tok.Data, Tok.Length); 703 } 704 705 void print(raw_ostream &OS) const override; 706 707 static std::unique_ptr<PPCOperand> CreateToken(StringRef Str, SMLoc S, 708 bool IsPPC64) { 709 auto Op = make_unique<PPCOperand>(Token); 710 Op->Tok.Data = Str.data(); 711 Op->Tok.Length = Str.size(); 712 Op->StartLoc = S; 713 Op->EndLoc = S; 714 Op->IsPPC64 = IsPPC64; 715 return Op; 716 } 717 718 static std::unique_ptr<PPCOperand> 719 CreateTokenWithStringCopy(StringRef Str, SMLoc S, bool IsPPC64) { 720 // Allocate extra memory for the string and copy it. 721 // FIXME: This is incorrect, Operands are owned by unique_ptr with a default 722 // deleter which will destroy them by simply using "delete", not correctly 723 // calling operator delete on this extra memory after calling the dtor 724 // explicitly. 725 void *Mem = ::operator new(sizeof(PPCOperand) + Str.size()); 726 std::unique_ptr<PPCOperand> Op(new (Mem) PPCOperand(Token)); 727 Op->Tok.Data = reinterpret_cast<const char *>(Op.get() + 1); 728 Op->Tok.Length = Str.size(); 729 std::memcpy(const_cast<char *>(Op->Tok.Data), Str.data(), Str.size()); 730 Op->StartLoc = S; 731 Op->EndLoc = S; 732 Op->IsPPC64 = IsPPC64; 733 return Op; 734 } 735 736 static std::unique_ptr<PPCOperand> CreateImm(int64_t Val, SMLoc S, SMLoc E, 737 bool IsPPC64) { 738 auto Op = make_unique<PPCOperand>(Immediate); 739 Op->Imm.Val = Val; 740 Op->StartLoc = S; 741 Op->EndLoc = E; 742 Op->IsPPC64 = IsPPC64; 743 return Op; 744 } 745 746 static std::unique_ptr<PPCOperand> CreateExpr(const MCExpr *Val, SMLoc S, 747 SMLoc E, bool IsPPC64) { 748 auto Op = make_unique<PPCOperand>(Expression); 749 Op->Expr.Val = Val; 750 Op->Expr.CRVal = EvaluateCRExpr(Val); 751 Op->StartLoc = S; 752 Op->EndLoc = E; 753 Op->IsPPC64 = IsPPC64; 754 return Op; 755 } 756 757 static std::unique_ptr<PPCOperand> 758 CreateTLSReg(const MCSymbolRefExpr *Sym, SMLoc S, SMLoc E, bool IsPPC64) { 759 auto Op = make_unique<PPCOperand>(TLSRegister); 760 Op->TLSReg.Sym = Sym; 761 Op->StartLoc = S; 762 Op->EndLoc = E; 763 Op->IsPPC64 = IsPPC64; 764 return Op; 765 } 766 767 static std::unique_ptr<PPCOperand> 768 CreateContextImm(int64_t Val, SMLoc S, SMLoc E, bool IsPPC64) { 769 auto Op = make_unique<PPCOperand>(ContextImmediate); 770 Op->Imm.Val = Val; 771 Op->StartLoc = S; 772 Op->EndLoc = E; 773 Op->IsPPC64 = IsPPC64; 774 return Op; 775 } 776 777 static std::unique_ptr<PPCOperand> 778 CreateFromMCExpr(const MCExpr *Val, SMLoc S, SMLoc E, bool IsPPC64) { 779 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Val)) 780 return CreateImm(CE->getValue(), S, E, IsPPC64); 781 782 if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(Val)) 783 if (SRE->getKind() == MCSymbolRefExpr::VK_PPC_TLS) 784 return CreateTLSReg(SRE, S, E, IsPPC64); 785 786 if (const PPCMCExpr *TE = dyn_cast<PPCMCExpr>(Val)) { 787 int64_t Res; 788 if (TE->evaluateAsConstant(Res)) 789 return CreateContextImm(Res, S, E, IsPPC64); 790 } 791 792 return CreateExpr(Val, S, E, IsPPC64); 793 } 794 }; 795 796 } // end anonymous namespace. 797 798 void PPCOperand::print(raw_ostream &OS) const { 799 switch (Kind) { 800 case Token: 801 OS << "'" << getToken() << "'"; 802 break; 803 case Immediate: 804 case ContextImmediate: 805 OS << getImm(); 806 break; 807 case Expression: 808 OS << *getExpr(); 809 break; 810 case TLSRegister: 811 OS << *getTLSReg(); 812 break; 813 } 814 } 815 816 static void 817 addNegOperand(MCInst &Inst, MCOperand &Op, MCContext &Ctx) { 818 if (Op.isImm()) { 819 Inst.addOperand(MCOperand::createImm(-Op.getImm())); 820 return; 821 } 822 const MCExpr *Expr = Op.getExpr(); 823 if (const MCUnaryExpr *UnExpr = dyn_cast<MCUnaryExpr>(Expr)) { 824 if (UnExpr->getOpcode() == MCUnaryExpr::Minus) { 825 Inst.addOperand(MCOperand::createExpr(UnExpr->getSubExpr())); 826 return; 827 } 828 } else if (const MCBinaryExpr *BinExpr = dyn_cast<MCBinaryExpr>(Expr)) { 829 if (BinExpr->getOpcode() == MCBinaryExpr::Sub) { 830 const MCExpr *NE = MCBinaryExpr::createSub(BinExpr->getRHS(), 831 BinExpr->getLHS(), Ctx); 832 Inst.addOperand(MCOperand::createExpr(NE)); 833 return; 834 } 835 } 836 Inst.addOperand(MCOperand::createExpr(MCUnaryExpr::createMinus(Expr, Ctx))); 837 } 838 839 void PPCAsmParser::ProcessInstruction(MCInst &Inst, 840 const OperandVector &Operands) { 841 int Opcode = Inst.getOpcode(); 842 switch (Opcode) { 843 case PPC::DCBTx: 844 case PPC::DCBTT: 845 case PPC::DCBTSTx: 846 case PPC::DCBTSTT: { 847 MCInst TmpInst; 848 TmpInst.setOpcode((Opcode == PPC::DCBTx || Opcode == PPC::DCBTT) ? 849 PPC::DCBT : PPC::DCBTST); 850 TmpInst.addOperand(MCOperand::createImm( 851 (Opcode == PPC::DCBTx || Opcode == PPC::DCBTSTx) ? 0 : 16)); 852 TmpInst.addOperand(Inst.getOperand(0)); 853 TmpInst.addOperand(Inst.getOperand(1)); 854 Inst = TmpInst; 855 break; 856 } 857 case PPC::DCBTCT: 858 case PPC::DCBTDS: { 859 MCInst TmpInst; 860 TmpInst.setOpcode(PPC::DCBT); 861 TmpInst.addOperand(Inst.getOperand(2)); 862 TmpInst.addOperand(Inst.getOperand(0)); 863 TmpInst.addOperand(Inst.getOperand(1)); 864 Inst = TmpInst; 865 break; 866 } 867 case PPC::DCBTSTCT: 868 case PPC::DCBTSTDS: { 869 MCInst TmpInst; 870 TmpInst.setOpcode(PPC::DCBTST); 871 TmpInst.addOperand(Inst.getOperand(2)); 872 TmpInst.addOperand(Inst.getOperand(0)); 873 TmpInst.addOperand(Inst.getOperand(1)); 874 Inst = TmpInst; 875 break; 876 } 877 case PPC::LAx: { 878 MCInst TmpInst; 879 TmpInst.setOpcode(PPC::LA); 880 TmpInst.addOperand(Inst.getOperand(0)); 881 TmpInst.addOperand(Inst.getOperand(2)); 882 TmpInst.addOperand(Inst.getOperand(1)); 883 Inst = TmpInst; 884 break; 885 } 886 case PPC::SUBI: { 887 MCInst TmpInst; 888 TmpInst.setOpcode(PPC::ADDI); 889 TmpInst.addOperand(Inst.getOperand(0)); 890 TmpInst.addOperand(Inst.getOperand(1)); 891 addNegOperand(TmpInst, Inst.getOperand(2), getContext()); 892 Inst = TmpInst; 893 break; 894 } 895 case PPC::SUBIS: { 896 MCInst TmpInst; 897 TmpInst.setOpcode(PPC::ADDIS); 898 TmpInst.addOperand(Inst.getOperand(0)); 899 TmpInst.addOperand(Inst.getOperand(1)); 900 addNegOperand(TmpInst, Inst.getOperand(2), getContext()); 901 Inst = TmpInst; 902 break; 903 } 904 case PPC::SUBIC: { 905 MCInst TmpInst; 906 TmpInst.setOpcode(PPC::ADDIC); 907 TmpInst.addOperand(Inst.getOperand(0)); 908 TmpInst.addOperand(Inst.getOperand(1)); 909 addNegOperand(TmpInst, Inst.getOperand(2), getContext()); 910 Inst = TmpInst; 911 break; 912 } 913 case PPC::SUBICo: { 914 MCInst TmpInst; 915 TmpInst.setOpcode(PPC::ADDICo); 916 TmpInst.addOperand(Inst.getOperand(0)); 917 TmpInst.addOperand(Inst.getOperand(1)); 918 addNegOperand(TmpInst, Inst.getOperand(2), getContext()); 919 Inst = TmpInst; 920 break; 921 } 922 case PPC::EXTLWI: 923 case PPC::EXTLWIo: { 924 MCInst TmpInst; 925 int64_t N = Inst.getOperand(2).getImm(); 926 int64_t B = Inst.getOperand(3).getImm(); 927 TmpInst.setOpcode(Opcode == PPC::EXTLWI? PPC::RLWINM : PPC::RLWINMo); 928 TmpInst.addOperand(Inst.getOperand(0)); 929 TmpInst.addOperand(Inst.getOperand(1)); 930 TmpInst.addOperand(MCOperand::createImm(B)); 931 TmpInst.addOperand(MCOperand::createImm(0)); 932 TmpInst.addOperand(MCOperand::createImm(N - 1)); 933 Inst = TmpInst; 934 break; 935 } 936 case PPC::EXTRWI: 937 case PPC::EXTRWIo: { 938 MCInst TmpInst; 939 int64_t N = Inst.getOperand(2).getImm(); 940 int64_t B = Inst.getOperand(3).getImm(); 941 TmpInst.setOpcode(Opcode == PPC::EXTRWI? PPC::RLWINM : PPC::RLWINMo); 942 TmpInst.addOperand(Inst.getOperand(0)); 943 TmpInst.addOperand(Inst.getOperand(1)); 944 TmpInst.addOperand(MCOperand::createImm(B + N)); 945 TmpInst.addOperand(MCOperand::createImm(32 - N)); 946 TmpInst.addOperand(MCOperand::createImm(31)); 947 Inst = TmpInst; 948 break; 949 } 950 case PPC::INSLWI: 951 case PPC::INSLWIo: { 952 MCInst TmpInst; 953 int64_t N = Inst.getOperand(2).getImm(); 954 int64_t B = Inst.getOperand(3).getImm(); 955 TmpInst.setOpcode(Opcode == PPC::INSLWI? PPC::RLWIMI : PPC::RLWIMIo); 956 TmpInst.addOperand(Inst.getOperand(0)); 957 TmpInst.addOperand(Inst.getOperand(0)); 958 TmpInst.addOperand(Inst.getOperand(1)); 959 TmpInst.addOperand(MCOperand::createImm(32 - B)); 960 TmpInst.addOperand(MCOperand::createImm(B)); 961 TmpInst.addOperand(MCOperand::createImm((B + N) - 1)); 962 Inst = TmpInst; 963 break; 964 } 965 case PPC::INSRWI: 966 case PPC::INSRWIo: { 967 MCInst TmpInst; 968 int64_t N = Inst.getOperand(2).getImm(); 969 int64_t B = Inst.getOperand(3).getImm(); 970 TmpInst.setOpcode(Opcode == PPC::INSRWI? PPC::RLWIMI : PPC::RLWIMIo); 971 TmpInst.addOperand(Inst.getOperand(0)); 972 TmpInst.addOperand(Inst.getOperand(0)); 973 TmpInst.addOperand(Inst.getOperand(1)); 974 TmpInst.addOperand(MCOperand::createImm(32 - (B + N))); 975 TmpInst.addOperand(MCOperand::createImm(B)); 976 TmpInst.addOperand(MCOperand::createImm((B + N) - 1)); 977 Inst = TmpInst; 978 break; 979 } 980 case PPC::ROTRWI: 981 case PPC::ROTRWIo: { 982 MCInst TmpInst; 983 int64_t N = Inst.getOperand(2).getImm(); 984 TmpInst.setOpcode(Opcode == PPC::ROTRWI? PPC::RLWINM : PPC::RLWINMo); 985 TmpInst.addOperand(Inst.getOperand(0)); 986 TmpInst.addOperand(Inst.getOperand(1)); 987 TmpInst.addOperand(MCOperand::createImm(32 - N)); 988 TmpInst.addOperand(MCOperand::createImm(0)); 989 TmpInst.addOperand(MCOperand::createImm(31)); 990 Inst = TmpInst; 991 break; 992 } 993 case PPC::SLWI: 994 case PPC::SLWIo: { 995 MCInst TmpInst; 996 int64_t N = Inst.getOperand(2).getImm(); 997 TmpInst.setOpcode(Opcode == PPC::SLWI? PPC::RLWINM : PPC::RLWINMo); 998 TmpInst.addOperand(Inst.getOperand(0)); 999 TmpInst.addOperand(Inst.getOperand(1)); 1000 TmpInst.addOperand(MCOperand::createImm(N)); 1001 TmpInst.addOperand(MCOperand::createImm(0)); 1002 TmpInst.addOperand(MCOperand::createImm(31 - N)); 1003 Inst = TmpInst; 1004 break; 1005 } 1006 case PPC::SRWI: 1007 case PPC::SRWIo: { 1008 MCInst TmpInst; 1009 int64_t N = Inst.getOperand(2).getImm(); 1010 TmpInst.setOpcode(Opcode == PPC::SRWI? PPC::RLWINM : PPC::RLWINMo); 1011 TmpInst.addOperand(Inst.getOperand(0)); 1012 TmpInst.addOperand(Inst.getOperand(1)); 1013 TmpInst.addOperand(MCOperand::createImm(32 - N)); 1014 TmpInst.addOperand(MCOperand::createImm(N)); 1015 TmpInst.addOperand(MCOperand::createImm(31)); 1016 Inst = TmpInst; 1017 break; 1018 } 1019 case PPC::CLRRWI: 1020 case PPC::CLRRWIo: { 1021 MCInst TmpInst; 1022 int64_t N = Inst.getOperand(2).getImm(); 1023 TmpInst.setOpcode(Opcode == PPC::CLRRWI? PPC::RLWINM : PPC::RLWINMo); 1024 TmpInst.addOperand(Inst.getOperand(0)); 1025 TmpInst.addOperand(Inst.getOperand(1)); 1026 TmpInst.addOperand(MCOperand::createImm(0)); 1027 TmpInst.addOperand(MCOperand::createImm(0)); 1028 TmpInst.addOperand(MCOperand::createImm(31 - N)); 1029 Inst = TmpInst; 1030 break; 1031 } 1032 case PPC::CLRLSLWI: 1033 case PPC::CLRLSLWIo: { 1034 MCInst TmpInst; 1035 int64_t B = Inst.getOperand(2).getImm(); 1036 int64_t N = Inst.getOperand(3).getImm(); 1037 TmpInst.setOpcode(Opcode == PPC::CLRLSLWI? PPC::RLWINM : PPC::RLWINMo); 1038 TmpInst.addOperand(Inst.getOperand(0)); 1039 TmpInst.addOperand(Inst.getOperand(1)); 1040 TmpInst.addOperand(MCOperand::createImm(N)); 1041 TmpInst.addOperand(MCOperand::createImm(B - N)); 1042 TmpInst.addOperand(MCOperand::createImm(31 - N)); 1043 Inst = TmpInst; 1044 break; 1045 } 1046 case PPC::EXTLDI: 1047 case PPC::EXTLDIo: { 1048 MCInst TmpInst; 1049 int64_t N = Inst.getOperand(2).getImm(); 1050 int64_t B = Inst.getOperand(3).getImm(); 1051 TmpInst.setOpcode(Opcode == PPC::EXTLDI? PPC::RLDICR : PPC::RLDICRo); 1052 TmpInst.addOperand(Inst.getOperand(0)); 1053 TmpInst.addOperand(Inst.getOperand(1)); 1054 TmpInst.addOperand(MCOperand::createImm(B)); 1055 TmpInst.addOperand(MCOperand::createImm(N - 1)); 1056 Inst = TmpInst; 1057 break; 1058 } 1059 case PPC::EXTRDI: 1060 case PPC::EXTRDIo: { 1061 MCInst TmpInst; 1062 int64_t N = Inst.getOperand(2).getImm(); 1063 int64_t B = Inst.getOperand(3).getImm(); 1064 TmpInst.setOpcode(Opcode == PPC::EXTRDI? PPC::RLDICL : PPC::RLDICLo); 1065 TmpInst.addOperand(Inst.getOperand(0)); 1066 TmpInst.addOperand(Inst.getOperand(1)); 1067 TmpInst.addOperand(MCOperand::createImm(B + N)); 1068 TmpInst.addOperand(MCOperand::createImm(64 - N)); 1069 Inst = TmpInst; 1070 break; 1071 } 1072 case PPC::INSRDI: 1073 case PPC::INSRDIo: { 1074 MCInst TmpInst; 1075 int64_t N = Inst.getOperand(2).getImm(); 1076 int64_t B = Inst.getOperand(3).getImm(); 1077 TmpInst.setOpcode(Opcode == PPC::INSRDI? PPC::RLDIMI : PPC::RLDIMIo); 1078 TmpInst.addOperand(Inst.getOperand(0)); 1079 TmpInst.addOperand(Inst.getOperand(0)); 1080 TmpInst.addOperand(Inst.getOperand(1)); 1081 TmpInst.addOperand(MCOperand::createImm(64 - (B + N))); 1082 TmpInst.addOperand(MCOperand::createImm(B)); 1083 Inst = TmpInst; 1084 break; 1085 } 1086 case PPC::ROTRDI: 1087 case PPC::ROTRDIo: { 1088 MCInst TmpInst; 1089 int64_t N = Inst.getOperand(2).getImm(); 1090 TmpInst.setOpcode(Opcode == PPC::ROTRDI? PPC::RLDICL : PPC::RLDICLo); 1091 TmpInst.addOperand(Inst.getOperand(0)); 1092 TmpInst.addOperand(Inst.getOperand(1)); 1093 TmpInst.addOperand(MCOperand::createImm(64 - N)); 1094 TmpInst.addOperand(MCOperand::createImm(0)); 1095 Inst = TmpInst; 1096 break; 1097 } 1098 case PPC::SLDI: 1099 case PPC::SLDIo: { 1100 MCInst TmpInst; 1101 int64_t N = Inst.getOperand(2).getImm(); 1102 TmpInst.setOpcode(Opcode == PPC::SLDI? PPC::RLDICR : PPC::RLDICRo); 1103 TmpInst.addOperand(Inst.getOperand(0)); 1104 TmpInst.addOperand(Inst.getOperand(1)); 1105 TmpInst.addOperand(MCOperand::createImm(N)); 1106 TmpInst.addOperand(MCOperand::createImm(63 - N)); 1107 Inst = TmpInst; 1108 break; 1109 } 1110 case PPC::SRDI: 1111 case PPC::SRDIo: { 1112 MCInst TmpInst; 1113 int64_t N = Inst.getOperand(2).getImm(); 1114 TmpInst.setOpcode(Opcode == PPC::SRDI? PPC::RLDICL : PPC::RLDICLo); 1115 TmpInst.addOperand(Inst.getOperand(0)); 1116 TmpInst.addOperand(Inst.getOperand(1)); 1117 TmpInst.addOperand(MCOperand::createImm(64 - N)); 1118 TmpInst.addOperand(MCOperand::createImm(N)); 1119 Inst = TmpInst; 1120 break; 1121 } 1122 case PPC::CLRRDI: 1123 case PPC::CLRRDIo: { 1124 MCInst TmpInst; 1125 int64_t N = Inst.getOperand(2).getImm(); 1126 TmpInst.setOpcode(Opcode == PPC::CLRRDI? PPC::RLDICR : PPC::RLDICRo); 1127 TmpInst.addOperand(Inst.getOperand(0)); 1128 TmpInst.addOperand(Inst.getOperand(1)); 1129 TmpInst.addOperand(MCOperand::createImm(0)); 1130 TmpInst.addOperand(MCOperand::createImm(63 - N)); 1131 Inst = TmpInst; 1132 break; 1133 } 1134 case PPC::CLRLSLDI: 1135 case PPC::CLRLSLDIo: { 1136 MCInst TmpInst; 1137 int64_t B = Inst.getOperand(2).getImm(); 1138 int64_t N = Inst.getOperand(3).getImm(); 1139 TmpInst.setOpcode(Opcode == PPC::CLRLSLDI? PPC::RLDIC : PPC::RLDICo); 1140 TmpInst.addOperand(Inst.getOperand(0)); 1141 TmpInst.addOperand(Inst.getOperand(1)); 1142 TmpInst.addOperand(MCOperand::createImm(N)); 1143 TmpInst.addOperand(MCOperand::createImm(B - N)); 1144 Inst = TmpInst; 1145 break; 1146 } 1147 case PPC::RLWINMbm: 1148 case PPC::RLWINMobm: { 1149 unsigned MB, ME; 1150 int64_t BM = Inst.getOperand(3).getImm(); 1151 if (!isRunOfOnes(BM, MB, ME)) 1152 break; 1153 1154 MCInst TmpInst; 1155 TmpInst.setOpcode(Opcode == PPC::RLWINMbm ? PPC::RLWINM : PPC::RLWINMo); 1156 TmpInst.addOperand(Inst.getOperand(0)); 1157 TmpInst.addOperand(Inst.getOperand(1)); 1158 TmpInst.addOperand(Inst.getOperand(2)); 1159 TmpInst.addOperand(MCOperand::createImm(MB)); 1160 TmpInst.addOperand(MCOperand::createImm(ME)); 1161 Inst = TmpInst; 1162 break; 1163 } 1164 case PPC::RLWIMIbm: 1165 case PPC::RLWIMIobm: { 1166 unsigned MB, ME; 1167 int64_t BM = Inst.getOperand(3).getImm(); 1168 if (!isRunOfOnes(BM, MB, ME)) 1169 break; 1170 1171 MCInst TmpInst; 1172 TmpInst.setOpcode(Opcode == PPC::RLWIMIbm ? PPC::RLWIMI : PPC::RLWIMIo); 1173 TmpInst.addOperand(Inst.getOperand(0)); 1174 TmpInst.addOperand(Inst.getOperand(0)); // The tied operand. 1175 TmpInst.addOperand(Inst.getOperand(1)); 1176 TmpInst.addOperand(Inst.getOperand(2)); 1177 TmpInst.addOperand(MCOperand::createImm(MB)); 1178 TmpInst.addOperand(MCOperand::createImm(ME)); 1179 Inst = TmpInst; 1180 break; 1181 } 1182 case PPC::RLWNMbm: 1183 case PPC::RLWNMobm: { 1184 unsigned MB, ME; 1185 int64_t BM = Inst.getOperand(3).getImm(); 1186 if (!isRunOfOnes(BM, MB, ME)) 1187 break; 1188 1189 MCInst TmpInst; 1190 TmpInst.setOpcode(Opcode == PPC::RLWNMbm ? PPC::RLWNM : PPC::RLWNMo); 1191 TmpInst.addOperand(Inst.getOperand(0)); 1192 TmpInst.addOperand(Inst.getOperand(1)); 1193 TmpInst.addOperand(Inst.getOperand(2)); 1194 TmpInst.addOperand(MCOperand::createImm(MB)); 1195 TmpInst.addOperand(MCOperand::createImm(ME)); 1196 Inst = TmpInst; 1197 break; 1198 } 1199 case PPC::MFTB: { 1200 if (getSTI().getFeatureBits()[PPC::FeatureMFTB]) { 1201 assert(Inst.getNumOperands() == 2 && "Expecting two operands"); 1202 Inst.setOpcode(PPC::MFSPR); 1203 } 1204 break; 1205 } 1206 case PPC::CP_COPYx: 1207 case PPC::CP_COPY_FIRST: { 1208 MCInst TmpInst; 1209 TmpInst.setOpcode(PPC::CP_COPY); 1210 TmpInst.addOperand(Inst.getOperand(0)); 1211 TmpInst.addOperand(Inst.getOperand(1)); 1212 TmpInst.addOperand(MCOperand::createImm(Opcode == PPC::CP_COPYx ? 0 : 1)); 1213 1214 Inst = TmpInst; 1215 break; 1216 } 1217 case PPC::CP_PASTEx : 1218 case PPC::CP_PASTE_LAST: { 1219 MCInst TmpInst; 1220 TmpInst.setOpcode(Opcode == PPC::CP_PASTEx ? 1221 PPC::CP_PASTE : PPC::CP_PASTEo); 1222 TmpInst.addOperand(Inst.getOperand(0)); 1223 TmpInst.addOperand(Inst.getOperand(1)); 1224 TmpInst.addOperand(MCOperand::createImm(Opcode == PPC::CP_PASTEx ? 0 : 1)); 1225 1226 Inst = TmpInst; 1227 break; 1228 } 1229 } 1230 } 1231 1232 bool PPCAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, 1233 OperandVector &Operands, 1234 MCStreamer &Out, uint64_t &ErrorInfo, 1235 bool MatchingInlineAsm) { 1236 MCInst Inst; 1237 1238 switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) { 1239 case Match_Success: 1240 // Post-process instructions (typically extended mnemonics) 1241 ProcessInstruction(Inst, Operands); 1242 Inst.setLoc(IDLoc); 1243 Out.EmitInstruction(Inst, getSTI()); 1244 return false; 1245 case Match_MissingFeature: 1246 return Error(IDLoc, "instruction use requires an option to be enabled"); 1247 case Match_MnemonicFail: 1248 return Error(IDLoc, "unrecognized instruction mnemonic"); 1249 case Match_InvalidOperand: { 1250 SMLoc ErrorLoc = IDLoc; 1251 if (ErrorInfo != ~0ULL) { 1252 if (ErrorInfo >= Operands.size()) 1253 return Error(IDLoc, "too few operands for instruction"); 1254 1255 ErrorLoc = ((PPCOperand &)*Operands[ErrorInfo]).getStartLoc(); 1256 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc; 1257 } 1258 1259 return Error(ErrorLoc, "invalid operand for instruction"); 1260 } 1261 } 1262 1263 llvm_unreachable("Implement any new match types added!"); 1264 } 1265 1266 bool PPCAsmParser:: 1267 MatchRegisterName(const AsmToken &Tok, unsigned &RegNo, int64_t &IntVal) { 1268 if (Tok.is(AsmToken::Identifier)) { 1269 StringRef Name = Tok.getString(); 1270 1271 if (Name.equals_lower("lr")) { 1272 RegNo = isPPC64()? PPC::LR8 : PPC::LR; 1273 IntVal = 8; 1274 return false; 1275 } else if (Name.equals_lower("ctr")) { 1276 RegNo = isPPC64()? PPC::CTR8 : PPC::CTR; 1277 IntVal = 9; 1278 return false; 1279 } else if (Name.equals_lower("vrsave")) { 1280 RegNo = PPC::VRSAVE; 1281 IntVal = 256; 1282 return false; 1283 } else if (Name.startswith_lower("r") && 1284 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) { 1285 RegNo = isPPC64()? XRegs[IntVal] : RRegs[IntVal]; 1286 return false; 1287 } else if (Name.startswith_lower("f") && 1288 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) { 1289 RegNo = FRegs[IntVal]; 1290 return false; 1291 } else if (Name.startswith_lower("vs") && 1292 !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 64) { 1293 RegNo = VSRegs[IntVal]; 1294 return false; 1295 } else if (Name.startswith_lower("v") && 1296 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) { 1297 RegNo = VRegs[IntVal]; 1298 return false; 1299 } else if (Name.startswith_lower("q") && 1300 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) { 1301 RegNo = QFRegs[IntVal]; 1302 return false; 1303 } else if (Name.startswith_lower("cr") && 1304 !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 8) { 1305 RegNo = CRRegs[IntVal]; 1306 return false; 1307 } 1308 } 1309 1310 return true; 1311 } 1312 1313 bool PPCAsmParser:: 1314 ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) { 1315 MCAsmParser &Parser = getParser(); 1316 const AsmToken &Tok = Parser.getTok(); 1317 StartLoc = Tok.getLoc(); 1318 EndLoc = Tok.getEndLoc(); 1319 RegNo = 0; 1320 int64_t IntVal; 1321 1322 if (!MatchRegisterName(Tok, RegNo, IntVal)) { 1323 Parser.Lex(); // Eat identifier token. 1324 return false; 1325 } 1326 1327 return Error(StartLoc, "invalid register name"); 1328 } 1329 1330 /// Extract \code @l/@ha \endcode modifier from expression. Recursively scan 1331 /// the expression and check for VK_PPC_LO/HI/HA 1332 /// symbol variants. If all symbols with modifier use the same 1333 /// variant, return the corresponding PPCMCExpr::VariantKind, 1334 /// and a modified expression using the default symbol variant. 1335 /// Otherwise, return NULL. 1336 const MCExpr *PPCAsmParser:: 1337 ExtractModifierFromExpr(const MCExpr *E, 1338 PPCMCExpr::VariantKind &Variant) { 1339 MCContext &Context = getParser().getContext(); 1340 Variant = PPCMCExpr::VK_PPC_None; 1341 1342 switch (E->getKind()) { 1343 case MCExpr::Target: 1344 case MCExpr::Constant: 1345 return nullptr; 1346 1347 case MCExpr::SymbolRef: { 1348 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E); 1349 1350 switch (SRE->getKind()) { 1351 case MCSymbolRefExpr::VK_PPC_LO: 1352 Variant = PPCMCExpr::VK_PPC_LO; 1353 break; 1354 case MCSymbolRefExpr::VK_PPC_HI: 1355 Variant = PPCMCExpr::VK_PPC_HI; 1356 break; 1357 case MCSymbolRefExpr::VK_PPC_HA: 1358 Variant = PPCMCExpr::VK_PPC_HA; 1359 break; 1360 case MCSymbolRefExpr::VK_PPC_HIGHER: 1361 Variant = PPCMCExpr::VK_PPC_HIGHER; 1362 break; 1363 case MCSymbolRefExpr::VK_PPC_HIGHERA: 1364 Variant = PPCMCExpr::VK_PPC_HIGHERA; 1365 break; 1366 case MCSymbolRefExpr::VK_PPC_HIGHEST: 1367 Variant = PPCMCExpr::VK_PPC_HIGHEST; 1368 break; 1369 case MCSymbolRefExpr::VK_PPC_HIGHESTA: 1370 Variant = PPCMCExpr::VK_PPC_HIGHESTA; 1371 break; 1372 default: 1373 return nullptr; 1374 } 1375 1376 return MCSymbolRefExpr::create(&SRE->getSymbol(), Context); 1377 } 1378 1379 case MCExpr::Unary: { 1380 const MCUnaryExpr *UE = cast<MCUnaryExpr>(E); 1381 const MCExpr *Sub = ExtractModifierFromExpr(UE->getSubExpr(), Variant); 1382 if (!Sub) 1383 return nullptr; 1384 return MCUnaryExpr::create(UE->getOpcode(), Sub, Context); 1385 } 1386 1387 case MCExpr::Binary: { 1388 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E); 1389 PPCMCExpr::VariantKind LHSVariant, RHSVariant; 1390 const MCExpr *LHS = ExtractModifierFromExpr(BE->getLHS(), LHSVariant); 1391 const MCExpr *RHS = ExtractModifierFromExpr(BE->getRHS(), RHSVariant); 1392 1393 if (!LHS && !RHS) 1394 return nullptr; 1395 1396 if (!LHS) LHS = BE->getLHS(); 1397 if (!RHS) RHS = BE->getRHS(); 1398 1399 if (LHSVariant == PPCMCExpr::VK_PPC_None) 1400 Variant = RHSVariant; 1401 else if (RHSVariant == PPCMCExpr::VK_PPC_None) 1402 Variant = LHSVariant; 1403 else if (LHSVariant == RHSVariant) 1404 Variant = LHSVariant; 1405 else 1406 return nullptr; 1407 1408 return MCBinaryExpr::create(BE->getOpcode(), LHS, RHS, Context); 1409 } 1410 } 1411 1412 llvm_unreachable("Invalid expression kind!"); 1413 } 1414 1415 /// Find all VK_TLSGD/VK_TLSLD symbol references in expression and replace 1416 /// them by VK_PPC_TLSGD/VK_PPC_TLSLD. This is necessary to avoid having 1417 /// _GLOBAL_OFFSET_TABLE_ created via ELFObjectWriter::RelocNeedsGOT. 1418 /// FIXME: This is a hack. 1419 const MCExpr *PPCAsmParser:: 1420 FixupVariantKind(const MCExpr *E) { 1421 MCContext &Context = getParser().getContext(); 1422 1423 switch (E->getKind()) { 1424 case MCExpr::Target: 1425 case MCExpr::Constant: 1426 return E; 1427 1428 case MCExpr::SymbolRef: { 1429 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E); 1430 MCSymbolRefExpr::VariantKind Variant = MCSymbolRefExpr::VK_None; 1431 1432 switch (SRE->getKind()) { 1433 case MCSymbolRefExpr::VK_TLSGD: 1434 Variant = MCSymbolRefExpr::VK_PPC_TLSGD; 1435 break; 1436 case MCSymbolRefExpr::VK_TLSLD: 1437 Variant = MCSymbolRefExpr::VK_PPC_TLSLD; 1438 break; 1439 default: 1440 return E; 1441 } 1442 return MCSymbolRefExpr::create(&SRE->getSymbol(), Variant, Context); 1443 } 1444 1445 case MCExpr::Unary: { 1446 const MCUnaryExpr *UE = cast<MCUnaryExpr>(E); 1447 const MCExpr *Sub = FixupVariantKind(UE->getSubExpr()); 1448 if (Sub == UE->getSubExpr()) 1449 return E; 1450 return MCUnaryExpr::create(UE->getOpcode(), Sub, Context); 1451 } 1452 1453 case MCExpr::Binary: { 1454 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E); 1455 const MCExpr *LHS = FixupVariantKind(BE->getLHS()); 1456 const MCExpr *RHS = FixupVariantKind(BE->getRHS()); 1457 if (LHS == BE->getLHS() && RHS == BE->getRHS()) 1458 return E; 1459 return MCBinaryExpr::create(BE->getOpcode(), LHS, RHS, Context); 1460 } 1461 } 1462 1463 llvm_unreachable("Invalid expression kind!"); 1464 } 1465 1466 /// ParseExpression. This differs from the default "parseExpression" in that 1467 /// it handles modifiers. 1468 bool PPCAsmParser:: 1469 ParseExpression(const MCExpr *&EVal) { 1470 1471 if (isDarwin()) 1472 return ParseDarwinExpression(EVal); 1473 1474 // (ELF Platforms) 1475 // Handle \code @l/@ha \endcode 1476 if (getParser().parseExpression(EVal)) 1477 return true; 1478 1479 EVal = FixupVariantKind(EVal); 1480 1481 PPCMCExpr::VariantKind Variant; 1482 const MCExpr *E = ExtractModifierFromExpr(EVal, Variant); 1483 if (E) 1484 EVal = PPCMCExpr::create(Variant, E, false, getParser().getContext()); 1485 1486 return false; 1487 } 1488 1489 /// ParseDarwinExpression. (MachO Platforms) 1490 /// This differs from the default "parseExpression" in that it handles detection 1491 /// of the \code hi16(), ha16() and lo16() \endcode modifiers. At present, 1492 /// parseExpression() doesn't recognise the modifiers when in the Darwin/MachO 1493 /// syntax form so it is done here. TODO: Determine if there is merit in 1494 /// arranging for this to be done at a higher level. 1495 bool PPCAsmParser:: 1496 ParseDarwinExpression(const MCExpr *&EVal) { 1497 MCAsmParser &Parser = getParser(); 1498 PPCMCExpr::VariantKind Variant = PPCMCExpr::VK_PPC_None; 1499 switch (getLexer().getKind()) { 1500 default: 1501 break; 1502 case AsmToken::Identifier: 1503 // Compiler-generated Darwin identifiers begin with L,l,_ or "; thus 1504 // something starting with any other char should be part of the 1505 // asm syntax. If handwritten asm includes an identifier like lo16, 1506 // then all bets are off - but no-one would do that, right? 1507 StringRef poss = Parser.getTok().getString(); 1508 if (poss.equals_lower("lo16")) { 1509 Variant = PPCMCExpr::VK_PPC_LO; 1510 } else if (poss.equals_lower("hi16")) { 1511 Variant = PPCMCExpr::VK_PPC_HI; 1512 } else if (poss.equals_lower("ha16")) { 1513 Variant = PPCMCExpr::VK_PPC_HA; 1514 } 1515 if (Variant != PPCMCExpr::VK_PPC_None) { 1516 Parser.Lex(); // Eat the xx16 1517 if (getLexer().isNot(AsmToken::LParen)) 1518 return Error(Parser.getTok().getLoc(), "expected '('"); 1519 Parser.Lex(); // Eat the '(' 1520 } 1521 break; 1522 } 1523 1524 if (getParser().parseExpression(EVal)) 1525 return true; 1526 1527 if (Variant != PPCMCExpr::VK_PPC_None) { 1528 if (getLexer().isNot(AsmToken::RParen)) 1529 return Error(Parser.getTok().getLoc(), "expected ')'"); 1530 Parser.Lex(); // Eat the ')' 1531 EVal = PPCMCExpr::create(Variant, EVal, false, getParser().getContext()); 1532 } 1533 return false; 1534 } 1535 1536 /// ParseOperand 1537 /// This handles registers in the form 'NN', '%rNN' for ELF platforms and 1538 /// rNN for MachO. 1539 bool PPCAsmParser::ParseOperand(OperandVector &Operands) { 1540 MCAsmParser &Parser = getParser(); 1541 SMLoc S = Parser.getTok().getLoc(); 1542 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 1543 const MCExpr *EVal; 1544 1545 // Attempt to parse the next token as an immediate 1546 switch (getLexer().getKind()) { 1547 // Special handling for register names. These are interpreted 1548 // as immediates corresponding to the register number. 1549 case AsmToken::Percent: 1550 Parser.Lex(); // Eat the '%'. 1551 unsigned RegNo; 1552 int64_t IntVal; 1553 if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) { 1554 Parser.Lex(); // Eat the identifier token. 1555 Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64())); 1556 return false; 1557 } 1558 return Error(S, "invalid register name"); 1559 1560 case AsmToken::Identifier: 1561 // Note that non-register-name identifiers from the compiler will begin 1562 // with '_', 'L'/'l' or '"'. Of course, handwritten asm could include 1563 // identifiers like r31foo - so we fall through in the event that parsing 1564 // a register name fails. 1565 if (isDarwin()) { 1566 unsigned RegNo; 1567 int64_t IntVal; 1568 if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) { 1569 Parser.Lex(); // Eat the identifier token. 1570 Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64())); 1571 return false; 1572 } 1573 } 1574 // Fall-through to process non-register-name identifiers as expression. 1575 // All other expressions 1576 case AsmToken::LParen: 1577 case AsmToken::Plus: 1578 case AsmToken::Minus: 1579 case AsmToken::Integer: 1580 case AsmToken::Dot: 1581 case AsmToken::Dollar: 1582 case AsmToken::Exclaim: 1583 case AsmToken::Tilde: 1584 if (!ParseExpression(EVal)) 1585 break; 1586 /* fall through */ 1587 default: 1588 return Error(S, "unknown operand"); 1589 } 1590 1591 // Push the parsed operand into the list of operands 1592 Operands.push_back(PPCOperand::CreateFromMCExpr(EVal, S, E, isPPC64())); 1593 1594 // Check whether this is a TLS call expression 1595 bool TLSCall = false; 1596 if (const MCSymbolRefExpr *Ref = dyn_cast<MCSymbolRefExpr>(EVal)) 1597 TLSCall = Ref->getSymbol().getName() == "__tls_get_addr"; 1598 1599 if (TLSCall && getLexer().is(AsmToken::LParen)) { 1600 const MCExpr *TLSSym; 1601 1602 Parser.Lex(); // Eat the '('. 1603 S = Parser.getTok().getLoc(); 1604 if (ParseExpression(TLSSym)) 1605 return Error(S, "invalid TLS call expression"); 1606 if (getLexer().isNot(AsmToken::RParen)) 1607 return Error(Parser.getTok().getLoc(), "missing ')'"); 1608 E = Parser.getTok().getLoc(); 1609 Parser.Lex(); // Eat the ')'. 1610 1611 Operands.push_back(PPCOperand::CreateFromMCExpr(TLSSym, S, E, isPPC64())); 1612 } 1613 1614 // Otherwise, check for D-form memory operands 1615 if (!TLSCall && getLexer().is(AsmToken::LParen)) { 1616 Parser.Lex(); // Eat the '('. 1617 S = Parser.getTok().getLoc(); 1618 1619 int64_t IntVal; 1620 switch (getLexer().getKind()) { 1621 case AsmToken::Percent: 1622 Parser.Lex(); // Eat the '%'. 1623 unsigned RegNo; 1624 if (MatchRegisterName(Parser.getTok(), RegNo, IntVal)) 1625 return Error(S, "invalid register name"); 1626 Parser.Lex(); // Eat the identifier token. 1627 break; 1628 1629 case AsmToken::Integer: 1630 if (!isDarwin()) { 1631 if (getParser().parseAbsoluteExpression(IntVal) || 1632 IntVal < 0 || IntVal > 31) 1633 return Error(S, "invalid register number"); 1634 } else { 1635 return Error(S, "unexpected integer value"); 1636 } 1637 break; 1638 1639 case AsmToken::Identifier: 1640 if (isDarwin()) { 1641 unsigned RegNo; 1642 if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) { 1643 Parser.Lex(); // Eat the identifier token. 1644 break; 1645 } 1646 } 1647 // Fall-through.. 1648 1649 default: 1650 return Error(S, "invalid memory operand"); 1651 } 1652 1653 if (getLexer().isNot(AsmToken::RParen)) 1654 return Error(Parser.getTok().getLoc(), "missing ')'"); 1655 E = Parser.getTok().getLoc(); 1656 Parser.Lex(); // Eat the ')'. 1657 1658 Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64())); 1659 } 1660 1661 return false; 1662 } 1663 1664 /// Parse an instruction mnemonic followed by its operands. 1665 bool PPCAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name, 1666 SMLoc NameLoc, OperandVector &Operands) { 1667 // The first operand is the token for the instruction name. 1668 // If the next character is a '+' or '-', we need to add it to the 1669 // instruction name, to match what TableGen is doing. 1670 std::string NewOpcode; 1671 if (getLexer().is(AsmToken::Plus)) { 1672 getLexer().Lex(); 1673 NewOpcode = Name; 1674 NewOpcode += '+'; 1675 Name = NewOpcode; 1676 } 1677 if (getLexer().is(AsmToken::Minus)) { 1678 getLexer().Lex(); 1679 NewOpcode = Name; 1680 NewOpcode += '-'; 1681 Name = NewOpcode; 1682 } 1683 // If the instruction ends in a '.', we need to create a separate 1684 // token for it, to match what TableGen is doing. 1685 size_t Dot = Name.find('.'); 1686 StringRef Mnemonic = Name.slice(0, Dot); 1687 if (!NewOpcode.empty()) // Underlying memory for Name is volatile. 1688 Operands.push_back( 1689 PPCOperand::CreateTokenWithStringCopy(Mnemonic, NameLoc, isPPC64())); 1690 else 1691 Operands.push_back(PPCOperand::CreateToken(Mnemonic, NameLoc, isPPC64())); 1692 if (Dot != StringRef::npos) { 1693 SMLoc DotLoc = SMLoc::getFromPointer(NameLoc.getPointer() + Dot); 1694 StringRef DotStr = Name.slice(Dot, StringRef::npos); 1695 if (!NewOpcode.empty()) // Underlying memory for Name is volatile. 1696 Operands.push_back( 1697 PPCOperand::CreateTokenWithStringCopy(DotStr, DotLoc, isPPC64())); 1698 else 1699 Operands.push_back(PPCOperand::CreateToken(DotStr, DotLoc, isPPC64())); 1700 } 1701 1702 // If there are no more operands then finish 1703 if (getLexer().is(AsmToken::EndOfStatement)) 1704 return false; 1705 1706 // Parse the first operand 1707 if (ParseOperand(Operands)) 1708 return true; 1709 1710 while (getLexer().isNot(AsmToken::EndOfStatement) && 1711 getLexer().is(AsmToken::Comma)) { 1712 // Consume the comma token 1713 Lex(); 1714 1715 // Parse the next operand 1716 if (ParseOperand(Operands)) 1717 return true; 1718 } 1719 1720 // We'll now deal with an unfortunate special case: the syntax for the dcbt 1721 // and dcbtst instructions differs for server vs. embedded cores. 1722 // The syntax for dcbt is: 1723 // dcbt ra, rb, th [server] 1724 // dcbt th, ra, rb [embedded] 1725 // where th can be omitted when it is 0. dcbtst is the same. We take the 1726 // server form to be the default, so swap the operands if we're parsing for 1727 // an embedded core (they'll be swapped again upon printing). 1728 if (getSTI().getFeatureBits()[PPC::FeatureBookE] && 1729 Operands.size() == 4 && 1730 (Name == "dcbt" || Name == "dcbtst")) { 1731 std::swap(Operands[1], Operands[3]); 1732 std::swap(Operands[2], Operands[1]); 1733 } 1734 1735 return false; 1736 } 1737 1738 /// ParseDirective parses the PPC specific directives 1739 bool PPCAsmParser::ParseDirective(AsmToken DirectiveID) { 1740 StringRef IDVal = DirectiveID.getIdentifier(); 1741 if (!isDarwin()) { 1742 if (IDVal == ".word") 1743 return ParseDirectiveWord(2, DirectiveID.getLoc()); 1744 if (IDVal == ".llong") 1745 return ParseDirectiveWord(8, DirectiveID.getLoc()); 1746 if (IDVal == ".tc") 1747 return ParseDirectiveTC(isPPC64()? 8 : 4, DirectiveID.getLoc()); 1748 if (IDVal == ".machine") 1749 return ParseDirectiveMachine(DirectiveID.getLoc()); 1750 if (IDVal == ".abiversion") 1751 return ParseDirectiveAbiVersion(DirectiveID.getLoc()); 1752 if (IDVal == ".localentry") 1753 return ParseDirectiveLocalEntry(DirectiveID.getLoc()); 1754 } else { 1755 if (IDVal == ".machine") 1756 return ParseDarwinDirectiveMachine(DirectiveID.getLoc()); 1757 } 1758 return true; 1759 } 1760 1761 /// ParseDirectiveWord 1762 /// ::= .word [ expression (, expression)* ] 1763 bool PPCAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) { 1764 MCAsmParser &Parser = getParser(); 1765 if (getLexer().isNot(AsmToken::EndOfStatement)) { 1766 for (;;) { 1767 const MCExpr *Value; 1768 SMLoc ExprLoc = getLexer().getLoc(); 1769 if (getParser().parseExpression(Value)) 1770 return false; 1771 1772 if (const auto *MCE = dyn_cast<MCConstantExpr>(Value)) { 1773 assert(Size <= 8 && "Invalid size"); 1774 uint64_t IntValue = MCE->getValue(); 1775 if (!isUIntN(8 * Size, IntValue) && !isIntN(8 * Size, IntValue)) 1776 return Error(ExprLoc, "literal value out of range for directive"); 1777 getStreamer().EmitIntValue(IntValue, Size); 1778 } else { 1779 getStreamer().EmitValue(Value, Size, ExprLoc); 1780 } 1781 1782 if (getLexer().is(AsmToken::EndOfStatement)) 1783 break; 1784 1785 if (getLexer().isNot(AsmToken::Comma)) 1786 return Error(L, "unexpected token in directive"); 1787 Parser.Lex(); 1788 } 1789 } 1790 1791 Parser.Lex(); 1792 return false; 1793 } 1794 1795 /// ParseDirectiveTC 1796 /// ::= .tc [ symbol (, expression)* ] 1797 bool PPCAsmParser::ParseDirectiveTC(unsigned Size, SMLoc L) { 1798 MCAsmParser &Parser = getParser(); 1799 // Skip TC symbol, which is only used with XCOFF. 1800 while (getLexer().isNot(AsmToken::EndOfStatement) 1801 && getLexer().isNot(AsmToken::Comma)) 1802 Parser.Lex(); 1803 if (getLexer().isNot(AsmToken::Comma)) { 1804 Error(L, "unexpected token in directive"); 1805 return false; 1806 } 1807 Parser.Lex(); 1808 1809 // Align to word size. 1810 getParser().getStreamer().EmitValueToAlignment(Size); 1811 1812 // Emit expressions. 1813 return ParseDirectiveWord(Size, L); 1814 } 1815 1816 /// ParseDirectiveMachine (ELF platforms) 1817 /// ::= .machine [ cpu | "push" | "pop" ] 1818 bool PPCAsmParser::ParseDirectiveMachine(SMLoc L) { 1819 MCAsmParser &Parser = getParser(); 1820 if (getLexer().isNot(AsmToken::Identifier) && 1821 getLexer().isNot(AsmToken::String)) { 1822 Error(L, "unexpected token in directive"); 1823 return false; 1824 } 1825 1826 StringRef CPU = Parser.getTok().getIdentifier(); 1827 Parser.Lex(); 1828 1829 // FIXME: Right now, the parser always allows any available 1830 // instruction, so the .machine directive is not useful. 1831 // Implement ".machine any" (by doing nothing) for the benefit 1832 // of existing assembler code. Likewise, we can then implement 1833 // ".machine push" and ".machine pop" as no-op. 1834 if (CPU != "any" && CPU != "push" && CPU != "pop") { 1835 Error(L, "unrecognized machine type"); 1836 return false; 1837 } 1838 1839 if (getLexer().isNot(AsmToken::EndOfStatement)) { 1840 Error(L, "unexpected token in directive"); 1841 return false; 1842 } 1843 PPCTargetStreamer &TStreamer = 1844 *static_cast<PPCTargetStreamer *>( 1845 getParser().getStreamer().getTargetStreamer()); 1846 TStreamer.emitMachine(CPU); 1847 1848 return false; 1849 } 1850 1851 /// ParseDarwinDirectiveMachine (Mach-o platforms) 1852 /// ::= .machine cpu-identifier 1853 bool PPCAsmParser::ParseDarwinDirectiveMachine(SMLoc L) { 1854 MCAsmParser &Parser = getParser(); 1855 if (getLexer().isNot(AsmToken::Identifier) && 1856 getLexer().isNot(AsmToken::String)) { 1857 Error(L, "unexpected token in directive"); 1858 return false; 1859 } 1860 1861 StringRef CPU = Parser.getTok().getIdentifier(); 1862 Parser.Lex(); 1863 1864 // FIXME: this is only the 'default' set of cpu variants. 1865 // However we don't act on this information at present, this is simply 1866 // allowing parsing to proceed with minimal sanity checking. 1867 if (CPU != "ppc7400" && CPU != "ppc" && CPU != "ppc64") { 1868 Error(L, "unrecognized cpu type"); 1869 return false; 1870 } 1871 1872 if (isPPC64() && (CPU == "ppc7400" || CPU == "ppc")) { 1873 Error(L, "wrong cpu type specified for 64bit"); 1874 return false; 1875 } 1876 if (!isPPC64() && CPU == "ppc64") { 1877 Error(L, "wrong cpu type specified for 32bit"); 1878 return false; 1879 } 1880 1881 if (getLexer().isNot(AsmToken::EndOfStatement)) { 1882 Error(L, "unexpected token in directive"); 1883 return false; 1884 } 1885 1886 return false; 1887 } 1888 1889 /// ParseDirectiveAbiVersion 1890 /// ::= .abiversion constant-expression 1891 bool PPCAsmParser::ParseDirectiveAbiVersion(SMLoc L) { 1892 int64_t AbiVersion; 1893 if (getParser().parseAbsoluteExpression(AbiVersion)){ 1894 Error(L, "expected constant expression"); 1895 return false; 1896 } 1897 if (getLexer().isNot(AsmToken::EndOfStatement)) { 1898 Error(L, "unexpected token in directive"); 1899 return false; 1900 } 1901 1902 PPCTargetStreamer &TStreamer = 1903 *static_cast<PPCTargetStreamer *>( 1904 getParser().getStreamer().getTargetStreamer()); 1905 TStreamer.emitAbiVersion(AbiVersion); 1906 1907 return false; 1908 } 1909 1910 /// ParseDirectiveLocalEntry 1911 /// ::= .localentry symbol, expression 1912 bool PPCAsmParser::ParseDirectiveLocalEntry(SMLoc L) { 1913 StringRef Name; 1914 if (getParser().parseIdentifier(Name)) { 1915 Error(L, "expected identifier in directive"); 1916 return false; 1917 } 1918 MCSymbolELF *Sym = cast<MCSymbolELF>(getContext().getOrCreateSymbol(Name)); 1919 1920 if (getLexer().isNot(AsmToken::Comma)) { 1921 Error(L, "unexpected token in directive"); 1922 return false; 1923 } 1924 Lex(); 1925 1926 const MCExpr *Expr; 1927 if (getParser().parseExpression(Expr)) { 1928 Error(L, "expected expression"); 1929 return false; 1930 } 1931 1932 if (getLexer().isNot(AsmToken::EndOfStatement)) { 1933 Error(L, "unexpected token in directive"); 1934 return false; 1935 } 1936 1937 PPCTargetStreamer &TStreamer = 1938 *static_cast<PPCTargetStreamer *>( 1939 getParser().getStreamer().getTargetStreamer()); 1940 TStreamer.emitLocalEntry(Sym, Expr); 1941 1942 return false; 1943 } 1944 1945 1946 1947 /// Force static initialization. 1948 extern "C" void LLVMInitializePowerPCAsmParser() { 1949 RegisterMCAsmParser<PPCAsmParser> A(ThePPC32Target); 1950 RegisterMCAsmParser<PPCAsmParser> B(ThePPC64Target); 1951 RegisterMCAsmParser<PPCAsmParser> C(ThePPC64LETarget); 1952 } 1953 1954 #define GET_REGISTER_MATCHER 1955 #define GET_MATCHER_IMPLEMENTATION 1956 #include "PPCGenAsmMatcher.inc" 1957 1958 // Define this matcher function after the auto-generated include so we 1959 // have the match class enum definitions. 1960 unsigned PPCAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp, 1961 unsigned Kind) { 1962 // If the kind is a token for a literal immediate, check if our asm 1963 // operand matches. This is for InstAliases which have a fixed-value 1964 // immediate in the syntax. 1965 int64_t ImmVal; 1966 switch (Kind) { 1967 case MCK_0: ImmVal = 0; break; 1968 case MCK_1: ImmVal = 1; break; 1969 case MCK_2: ImmVal = 2; break; 1970 case MCK_3: ImmVal = 3; break; 1971 case MCK_4: ImmVal = 4; break; 1972 case MCK_5: ImmVal = 5; break; 1973 case MCK_6: ImmVal = 6; break; 1974 case MCK_7: ImmVal = 7; break; 1975 default: return Match_InvalidOperand; 1976 } 1977 1978 PPCOperand &Op = static_cast<PPCOperand &>(AsmOp); 1979 if (Op.isImm() && Op.getImm() == ImmVal) 1980 return Match_Success; 1981 1982 return Match_InvalidOperand; 1983 } 1984 1985 const MCExpr * 1986 PPCAsmParser::applyModifierToExpr(const MCExpr *E, 1987 MCSymbolRefExpr::VariantKind Variant, 1988 MCContext &Ctx) { 1989 switch (Variant) { 1990 case MCSymbolRefExpr::VK_PPC_LO: 1991 return PPCMCExpr::create(PPCMCExpr::VK_PPC_LO, E, false, Ctx); 1992 case MCSymbolRefExpr::VK_PPC_HI: 1993 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HI, E, false, Ctx); 1994 case MCSymbolRefExpr::VK_PPC_HA: 1995 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HA, E, false, Ctx); 1996 case MCSymbolRefExpr::VK_PPC_HIGHER: 1997 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHER, E, false, Ctx); 1998 case MCSymbolRefExpr::VK_PPC_HIGHERA: 1999 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHERA, E, false, Ctx); 2000 case MCSymbolRefExpr::VK_PPC_HIGHEST: 2001 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHEST, E, false, Ctx); 2002 case MCSymbolRefExpr::VK_PPC_HIGHESTA: 2003 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHESTA, E, false, Ctx); 2004 default: 2005 return nullptr; 2006 } 2007 } 2008
