1 //===- WebAssemblyTargetMachine.cpp - Define TargetMachine for WebAssembly -==// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 /// 10 /// \file 11 /// \brief This file defines the WebAssembly-specific subclass of TargetMachine. 12 /// 13 //===----------------------------------------------------------------------===// 14 15 #include "WebAssembly.h" 16 #include "MCTargetDesc/WebAssemblyMCTargetDesc.h" 17 #include "WebAssemblyTargetMachine.h" 18 #include "WebAssemblyTargetObjectFile.h" 19 #include "WebAssemblyTargetTransformInfo.h" 20 #include "llvm/CodeGen/MachineFunctionPass.h" 21 #include "llvm/CodeGen/Passes.h" 22 #include "llvm/CodeGen/RegAllocRegistry.h" 23 #include "llvm/CodeGen/TargetPassConfig.h" 24 #include "llvm/IR/Function.h" 25 #include "llvm/Support/TargetRegistry.h" 26 #include "llvm/Target/TargetOptions.h" 27 #include "llvm/Transforms/Scalar.h" 28 using namespace llvm; 29 30 #define DEBUG_TYPE "wasm" 31 32 extern "C" void LLVMInitializeWebAssemblyTarget() { 33 // Register the target. 34 RegisterTargetMachine<WebAssemblyTargetMachine> X(TheWebAssemblyTarget32); 35 RegisterTargetMachine<WebAssemblyTargetMachine> Y(TheWebAssemblyTarget64); 36 } 37 38 //===----------------------------------------------------------------------===// 39 // WebAssembly Lowering public interface. 40 //===----------------------------------------------------------------------===// 41 42 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) { 43 if (!RM.hasValue()) 44 return Reloc::PIC_; 45 return *RM; 46 } 47 48 /// Create an WebAssembly architecture model. 49 /// 50 WebAssemblyTargetMachine::WebAssemblyTargetMachine( 51 const Target &T, const Triple &TT, StringRef CPU, StringRef FS, 52 const TargetOptions &Options, Optional<Reloc::Model> RM, 53 CodeModel::Model CM, CodeGenOpt::Level OL) 54 : LLVMTargetMachine(T, 55 TT.isArch64Bit() ? "e-m:e-p:64:64-i64:64-n32:64-S128" 56 : "e-m:e-p:32:32-i64:64-n32:64-S128", 57 TT, CPU, FS, Options, getEffectiveRelocModel(RM), 58 CM, OL), 59 TLOF(make_unique<WebAssemblyTargetObjectFile>()) { 60 // WebAssembly type-checks expressions, but a noreturn function with a return 61 // type that doesn't match the context will cause a check failure. So we lower 62 // LLVM 'unreachable' to ISD::TRAP and then lower that to WebAssembly's 63 // 'unreachable' expression which is meant for that case. 64 this->Options.TrapUnreachable = true; 65 66 initAsmInfo(); 67 68 // Note that we don't use setRequiresStructuredCFG(true). It disables 69 // optimizations than we're ok with, and want, such as critical edge 70 // splitting and tail merging. 71 } 72 73 WebAssemblyTargetMachine::~WebAssemblyTargetMachine() {} 74 75 const WebAssemblySubtarget * 76 WebAssemblyTargetMachine::getSubtargetImpl(const Function &F) const { 77 Attribute CPUAttr = F.getFnAttribute("target-cpu"); 78 Attribute FSAttr = F.getFnAttribute("target-features"); 79 80 std::string CPU = !CPUAttr.hasAttribute(Attribute::None) 81 ? CPUAttr.getValueAsString().str() 82 : TargetCPU; 83 std::string FS = !FSAttr.hasAttribute(Attribute::None) 84 ? FSAttr.getValueAsString().str() 85 : TargetFS; 86 87 auto &I = SubtargetMap[CPU + FS]; 88 if (!I) { 89 // This needs to be done before we create a new subtarget since any 90 // creation will depend on the TM and the code generation flags on the 91 // function that reside in TargetOptions. 92 resetTargetOptions(F); 93 I = llvm::make_unique<WebAssemblySubtarget>(TargetTriple, CPU, FS, *this); 94 } 95 return I.get(); 96 } 97 98 namespace { 99 /// WebAssembly Code Generator Pass Configuration Options. 100 class WebAssemblyPassConfig final : public TargetPassConfig { 101 public: 102 WebAssemblyPassConfig(WebAssemblyTargetMachine *TM, PassManagerBase &PM) 103 : TargetPassConfig(TM, PM) {} 104 105 WebAssemblyTargetMachine &getWebAssemblyTargetMachine() const { 106 return getTM<WebAssemblyTargetMachine>(); 107 } 108 109 FunctionPass *createTargetRegisterAllocator(bool) override; 110 111 void addIRPasses() override; 112 bool addInstSelector() override; 113 void addPostRegAlloc() override; 114 bool addGCPasses() override { return false; } 115 void addPreEmitPass() override; 116 }; 117 } // end anonymous namespace 118 119 TargetIRAnalysis WebAssemblyTargetMachine::getTargetIRAnalysis() { 120 return TargetIRAnalysis([this](const Function &F) { 121 return TargetTransformInfo(WebAssemblyTTIImpl(this, F)); 122 }); 123 } 124 125 TargetPassConfig * 126 WebAssemblyTargetMachine::createPassConfig(PassManagerBase &PM) { 127 return new WebAssemblyPassConfig(this, PM); 128 } 129 130 FunctionPass *WebAssemblyPassConfig::createTargetRegisterAllocator(bool) { 131 return nullptr; // No reg alloc 132 } 133 134 //===----------------------------------------------------------------------===// 135 // The following functions are called from lib/CodeGen/Passes.cpp to modify 136 // the CodeGen pass sequence. 137 //===----------------------------------------------------------------------===// 138 139 void WebAssemblyPassConfig::addIRPasses() { 140 if (TM->Options.ThreadModel == ThreadModel::Single) 141 // In "single" mode, atomics get lowered to non-atomics. 142 addPass(createLowerAtomicPass()); 143 else 144 // Expand some atomic operations. WebAssemblyTargetLowering has hooks which 145 // control specifically what gets lowered. 146 addPass(createAtomicExpandPass(TM)); 147 148 // Optimize "returned" function attributes. 149 if (getOptLevel() != CodeGenOpt::None) 150 addPass(createWebAssemblyOptimizeReturned()); 151 152 TargetPassConfig::addIRPasses(); 153 } 154 155 bool WebAssemblyPassConfig::addInstSelector() { 156 (void)TargetPassConfig::addInstSelector(); 157 addPass( 158 createWebAssemblyISelDag(getWebAssemblyTargetMachine(), getOptLevel())); 159 // Run the argument-move pass immediately after the ScheduleDAG scheduler 160 // so that we can fix up the ARGUMENT instructions before anything else 161 // sees them in the wrong place. 162 addPass(createWebAssemblyArgumentMove()); 163 // Set the p2align operands. This information is present during ISel, however 164 // it's inconvenient to collect. Collect it now, and update the immediate 165 // operands. 166 addPass(createWebAssemblySetP2AlignOperands()); 167 return false; 168 } 169 170 void WebAssemblyPassConfig::addPostRegAlloc() { 171 // TODO: The following CodeGen passes don't currently support code containing 172 // virtual registers. Consider removing their restrictions and re-enabling 173 // them. 174 175 // Has no asserts of its own, but was not written to handle virtual regs. 176 disablePass(&ShrinkWrapID); 177 178 // These functions all require the AllVRegsAllocated property. 179 disablePass(&MachineCopyPropagationID); 180 disablePass(&PostRASchedulerID); 181 disablePass(&FuncletLayoutID); 182 disablePass(&StackMapLivenessID); 183 disablePass(&LiveDebugValuesID); 184 disablePass(&PatchableFunctionID); 185 186 TargetPassConfig::addPostRegAlloc(); 187 } 188 189 void WebAssemblyPassConfig::addPreEmitPass() { 190 TargetPassConfig::addPreEmitPass(); 191 192 // Now that we have a prologue and epilogue and all frame indices are 193 // rewritten, eliminate SP and FP. This allows them to be stackified, 194 // colored, and numbered with the rest of the registers. 195 addPass(createWebAssemblyReplacePhysRegs()); 196 197 if (getOptLevel() != CodeGenOpt::None) { 198 // LiveIntervals isn't commonly run this late. Re-establish preconditions. 199 addPass(createWebAssemblyPrepareForLiveIntervals()); 200 201 // Depend on LiveIntervals and perform some optimizations on it. 202 addPass(createWebAssemblyOptimizeLiveIntervals()); 203 204 // Prepare store instructions for register stackifying. 205 addPass(createWebAssemblyStoreResults()); 206 207 // Mark registers as representing wasm's expression stack. This is a key 208 // code-compression technique in WebAssembly. We run this pass (and 209 // StoreResults above) very late, so that it sees as much code as possible, 210 // including code emitted by PEI and expanded by late tail duplication. 211 addPass(createWebAssemblyRegStackify()); 212 213 // Run the register coloring pass to reduce the total number of registers. 214 // This runs after stackification so that it doesn't consider registers 215 // that become stackified. 216 addPass(createWebAssemblyRegColoring()); 217 } 218 219 // Eliminate multiple-entry loops. 220 addPass(createWebAssemblyFixIrreducibleControlFlow()); 221 222 // Put the CFG in structured form; insert BLOCK and LOOP markers. 223 addPass(createWebAssemblyCFGStackify()); 224 225 // Lower br_unless into br_if. 226 addPass(createWebAssemblyLowerBrUnless()); 227 228 // Perform the very last peephole optimizations on the code. 229 if (getOptLevel() != CodeGenOpt::None) 230 addPass(createWebAssemblyPeephole()); 231 232 // Create a mapping from LLVM CodeGen virtual registers to wasm registers. 233 addPass(createWebAssemblyRegNumbering()); 234 } 235