1 ; Test 31-to-64 bit zero extensions. 2 ; 3 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s 4 5 ; Test register extension, starting with an i64. 6 define i64 @f1(i64 %a) { 7 ; CHECK-LABEL: f1: 8 ; CHECK: llgtr %r2, %r2 9 ; CHECK: br %r14 10 %ext = and i64 %a, 2147483647 11 ret i64 %ext 12 } 13 14 ; Test register extension, starting with an i32. 15 define i64 @f2(i32 %a) { 16 ; CHECK-LABEL: f2: 17 ; CHECK: llgtr %r2, %r2 18 ; CHECK: br %r14 19 %and = and i32 %a, 2147483647 20 %ext = zext i32 %and to i64 21 ret i64 %ext 22 } 23 24 ; ... and the other way around. 25 define i64 @f3(i32 %a) { 26 ; CHECK-LABEL: f3: 27 ; CHECK: llgtr %r2, %r2 28 ; CHECK: br %r14 29 %ext = zext i32 %a to i64 30 %and = and i64 %ext, 2147483647 31 ret i64 %and 32 } 33 34 ; Check LLGT with no displacement. 35 define i64 @f4(i32 *%src) { 36 ; CHECK-LABEL: f4: 37 ; CHECK: llgt %r2, 0(%r2) 38 ; CHECK: br %r14 39 %word = load i32, i32 *%src 40 %ext = zext i32 %word to i64 41 %and = and i64 %ext, 2147483647 42 ret i64 %and 43 } 44 45 ; ... and the other way around. 46 define i64 @f5(i32 *%src) { 47 ; CHECK-LABEL: f5: 48 ; CHECK: llgt %r2, 0(%r2) 49 ; CHECK: br %r14 50 %word = load i32, i32 *%src 51 %and = and i32 %word, 2147483647 52 %ext = zext i32 %and to i64 53 ret i64 %ext 54 } 55 56 ; Check the high end of the LLGT range. 57 define i64 @f6(i32 *%src) { 58 ; CHECK-LABEL: f6: 59 ; CHECK: llgt %r2, 524284(%r2) 60 ; CHECK: br %r14 61 %ptr = getelementptr i32, i32 *%src, i64 131071 62 %word = load i32, i32 *%ptr 63 %ext = zext i32 %word to i64 64 %and = and i64 %ext, 2147483647 65 ret i64 %and 66 } 67 68 ; Check the next word up, which needs separate address logic. 69 ; Other sequences besides this one would be OK. 70 define i64 @f7(i32 *%src) { 71 ; CHECK-LABEL: f7: 72 ; CHECK: agfi %r2, 524288 73 ; CHECK: llgt %r2, 0(%r2) 74 ; CHECK: br %r14 75 %ptr = getelementptr i32, i32 *%src, i64 131072 76 %word = load i32, i32 *%ptr 77 %ext = zext i32 %word to i64 78 %and = and i64 %ext, 2147483647 79 ret i64 %and 80 } 81 82 ; Check the high end of the negative LLGT range. 83 define i64 @f8(i32 *%src) { 84 ; CHECK-LABEL: f8: 85 ; CHECK: llgt %r2, -4(%r2) 86 ; CHECK: br %r14 87 %ptr = getelementptr i32, i32 *%src, i64 -1 88 %word = load i32, i32 *%ptr 89 %ext = zext i32 %word to i64 90 %and = and i64 %ext, 2147483647 91 ret i64 %and 92 } 93 94 ; Check the low end of the LLGT range. 95 define i64 @f9(i32 *%src) { 96 ; CHECK-LABEL: f9: 97 ; CHECK: llgt %r2, -524288(%r2) 98 ; CHECK: br %r14 99 %ptr = getelementptr i32, i32 *%src, i64 -131072 100 %word = load i32, i32 *%ptr 101 %ext = zext i32 %word to i64 102 %and = and i64 %ext, 2147483647 103 ret i64 %and 104 } 105 106 ; Check the next word down, which needs separate address logic. 107 ; Other sequences besides this one would be OK. 108 define i64 @f10(i32 *%src) { 109 ; CHECK-LABEL: f10: 110 ; CHECK: agfi %r2, -524292 111 ; CHECK: llgt %r2, 0(%r2) 112 ; CHECK: br %r14 113 %ptr = getelementptr i32, i32 *%src, i64 -131073 114 %word = load i32, i32 *%ptr 115 %ext = zext i32 %word to i64 116 %and = and i64 %ext, 2147483647 117 ret i64 %and 118 } 119 120 ; Check that LLGT allows an index. 121 define i64 @f11(i64 %src, i64 %index) { 122 ; CHECK-LABEL: f11: 123 ; CHECK: llgt %r2, 524287(%r3,%r2) 124 ; CHECK: br %r14 125 %add1 = add i64 %src, %index 126 %add2 = add i64 %add1, 524287 127 %ptr = inttoptr i64 %add2 to i32 * 128 %word = load i32, i32 *%ptr 129 %ext = zext i32 %word to i64 130 %and = and i64 %ext, 2147483647 131 ret i64 %and 132 } 133 134
