1 ; Test sequences that can use RISBG with a zeroed first operand. 2 ; The tests here assume that RISBLG isn't available. 3 ; 4 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s 5 6 ; Test an extraction of bit 0 from a right-shifted value. 7 define i32 @f1(i32 %foo) { 8 ; CHECK-LABEL: f1: 9 ; CHECK: risbg %r2, %r2, 63, 191, 54 10 ; CHECK: br %r14 11 %shr = lshr i32 %foo, 10 12 %and = and i32 %shr, 1 13 ret i32 %and 14 } 15 16 ; ...and again with i64. 17 define i64 @f2(i64 %foo) { 18 ; CHECK-LABEL: f2: 19 ; CHECK: risbg %r2, %r2, 63, 191, 54 20 ; CHECK: br %r14 21 %shr = lshr i64 %foo, 10 22 %and = and i64 %shr, 1 23 ret i64 %and 24 } 25 26 ; Test an extraction of other bits from a right-shifted value. 27 define i32 @f3(i32 %foo) { 28 ; CHECK-LABEL: f3: 29 ; CHECK: risbg %r2, %r2, 60, 189, 42 30 ; CHECK: br %r14 31 %shr = lshr i32 %foo, 22 32 %and = and i32 %shr, 12 33 ret i32 %and 34 } 35 36 ; ...and again with i64. 37 define i64 @f4(i64 %foo) { 38 ; CHECK-LABEL: f4: 39 ; CHECK: risbg %r2, %r2, 60, 189, 42 40 ; CHECK: br %r14 41 %shr = lshr i64 %foo, 22 42 %and = and i64 %shr, 12 43 ret i64 %and 44 } 45 46 ; Test an extraction of most bits from a right-shifted value. 47 ; The range should be reduced to exclude the zeroed high bits. 48 define i32 @f5(i32 %foo) { 49 ; CHECK-LABEL: f5: 50 ; CHECK: risbg %r2, %r2, 34, 188, 62 51 ; CHECK: br %r14 52 %shr = lshr i32 %foo, 2 53 %and = and i32 %shr, -8 54 ret i32 %and 55 } 56 57 ; ...and again with i64. 58 define i64 @f6(i64 %foo) { 59 ; CHECK-LABEL: f6: 60 ; CHECK: risbg %r2, %r2, 2, 188, 62 61 ; CHECK: br %r14 62 %shr = lshr i64 %foo, 2 63 %and = and i64 %shr, -8 64 ret i64 %and 65 } 66 67 ; Try the next value up (mask ....1111001). This needs a separate shift 68 ; and mask. 69 define i32 @f7(i32 %foo) { 70 ; CHECK-LABEL: f7: 71 ; CHECK: srl %r2, 2 72 ; CHECK: nill %r2, 65529 73 ; CHECK: br %r14 74 %shr = lshr i32 %foo, 2 75 %and = and i32 %shr, -7 76 ret i32 %and 77 } 78 79 ; ...and again with i64. 80 define i64 @f8(i64 %foo) { 81 ; CHECK-LABEL: f8: 82 ; CHECK: srlg %r2, %r2, 2 83 ; CHECK: nill %r2, 65529 84 ; CHECK: br %r14 85 %shr = lshr i64 %foo, 2 86 %and = and i64 %shr, -7 87 ret i64 %and 88 } 89 90 ; Test an extraction of bits from a left-shifted value. The range should 91 ; be reduced to exclude the zeroed low bits. 92 define i32 @f9(i32 %foo) { 93 ; CHECK-LABEL: f9: 94 ; CHECK: risbg %r2, %r2, 56, 189, 2 95 ; CHECK: br %r14 96 %shr = shl i32 %foo, 2 97 %and = and i32 %shr, 255 98 ret i32 %and 99 } 100 101 ; ...and again with i64. 102 define i64 @f10(i64 %foo) { 103 ; CHECK-LABEL: f10: 104 ; CHECK: risbg %r2, %r2, 56, 189, 2 105 ; CHECK: br %r14 106 %shr = shl i64 %foo, 2 107 %and = and i64 %shr, 255 108 ret i64 %and 109 } 110 111 ; Try a wrap-around mask (mask ....111100001111). This needs a separate shift 112 ; and mask. 113 define i32 @f11(i32 %foo) { 114 ; CHECK-LABEL: f11: 115 ; CHECK: sll %r2, 2 116 ; CHECK: nill %r2, 65295 117 ; CHECK: br %r14 118 %shr = shl i32 %foo, 2 119 %and = and i32 %shr, -241 120 ret i32 %and 121 } 122 123 ; ...and again with i64. 124 define i64 @f12(i64 %foo) { 125 ; CHECK-LABEL: f12: 126 ; CHECK: sllg %r2, %r2, 2 127 ; CHECK: nill %r2, 65295 128 ; CHECK: br %r14 129 %shr = shl i64 %foo, 2 130 %and = and i64 %shr, -241 131 ret i64 %and 132 } 133 134 ; Test an extraction from a rotated value, no mask wraparound. 135 ; This is equivalent to the lshr case, because the bits from the 136 ; shl are not used. 137 define i32 @f13(i32 %foo) { 138 ; CHECK-LABEL: f13: 139 ; CHECK: risbg %r2, %r2, 56, 188, 46 140 ; CHECK: br %r14 141 %parta = shl i32 %foo, 14 142 %partb = lshr i32 %foo, 18 143 %rotl = or i32 %parta, %partb 144 %and = and i32 %rotl, 248 145 ret i32 %and 146 } 147 148 ; ...and again with i64. 149 define i64 @f14(i64 %foo) { 150 ; CHECK-LABEL: f14: 151 ; CHECK: risbg %r2, %r2, 56, 188, 14 152 ; CHECK: br %r14 153 %parta = shl i64 %foo, 14 154 %partb = lshr i64 %foo, 50 155 %rotl = or i64 %parta, %partb 156 %and = and i64 %rotl, 248 157 ret i64 %and 158 } 159 160 ; Try a case in which only the bits from the shl are used. 161 define i32 @f15(i32 %foo) { 162 ; CHECK-LABEL: f15: 163 ; CHECK: risbg %r2, %r2, 47, 177, 14 164 ; CHECK: br %r14 165 %parta = shl i32 %foo, 14 166 %partb = lshr i32 %foo, 18 167 %rotl = or i32 %parta, %partb 168 %and = and i32 %rotl, 114688 169 ret i32 %and 170 } 171 172 ; ...and again with i64. 173 define i64 @f16(i64 %foo) { 174 ; CHECK-LABEL: f16: 175 ; CHECK: risbg %r2, %r2, 47, 177, 14 176 ; CHECK: br %r14 177 %parta = shl i64 %foo, 14 178 %partb = lshr i64 %foo, 50 179 %rotl = or i64 %parta, %partb 180 %and = and i64 %rotl, 114688 181 ret i64 %and 182 } 183 184 ; Test a 32-bit rotate in which both parts of the OR are needed. 185 ; This needs a separate shift and mask. 186 define i32 @f17(i32 %foo) { 187 ; CHECK-LABEL: f17: 188 ; CHECK: rll %r2, %r2, 4 189 ; CHECK: nilf %r2, 126 190 ; CHECK: br %r14 191 %parta = shl i32 %foo, 4 192 %partb = lshr i32 %foo, 28 193 %rotl = or i32 %parta, %partb 194 %and = and i32 %rotl, 126 195 ret i32 %and 196 } 197 198 ; ...and for i64, where RISBG should do the rotate too. 199 define i64 @f18(i64 %foo) { 200 ; CHECK-LABEL: f18: 201 ; CHECK: risbg %r2, %r2, 57, 190, 4 202 ; CHECK: br %r14 203 %parta = shl i64 %foo, 4 204 %partb = lshr i64 %foo, 60 205 %rotl = or i64 %parta, %partb 206 %and = and i64 %rotl, 126 207 ret i64 %and 208 } 209 210 ; Test an arithmetic shift right in which some of the sign bits are kept. 211 ; This needs a separate shift and mask. 212 define i32 @f19(i32 %foo) { 213 ; CHECK-LABEL: f19: 214 ; CHECK: sra %r2, 28 215 ; CHECK: nilf %r2, 30 216 ; CHECK: br %r14 217 %shr = ashr i32 %foo, 28 218 %and = and i32 %shr, 30 219 ret i32 %and 220 } 221 222 ; ...and again with i64. In this case RISBG is the best way of doing the AND. 223 define i64 @f20(i64 %foo) { 224 ; CHECK-LABEL: f20: 225 ; CHECK: srag [[REG:%r[0-5]]], %r2, 60 226 ; CHECK: risbg %r2, [[REG]], 59, 190, 0 227 ; CHECK: br %r14 228 %shr = ashr i64 %foo, 60 229 %and = and i64 %shr, 30 230 ret i64 %and 231 } 232 233 ; Now try an arithmetic right shift in which the sign bits aren't needed. 234 ; Introduce a second use of %shr so that the ashr doesn't decompose to 235 ; an lshr. 236 ; NOTE: the extra move to %r2 should not be needed (temporary FAIL) 237 define i32 @f21(i32 %foo, i32 *%dest) { 238 ; CHECK-LABEL: f21: 239 ; CHECK: risbg %r0, %r2, 60, 190, 36 240 ; CHECK: lr %r2, %r0 241 ; CHECK: br %r14 242 %shr = ashr i32 %foo, 28 243 store i32 %shr, i32 *%dest 244 %and = and i32 %shr, 14 245 ret i32 %and 246 } 247 248 ; ...and again with i64. 249 define i64 @f22(i64 %foo, i64 *%dest) { 250 ; CHECK-LABEL: f22: 251 ; CHECK: risbg %r2, %r2, 60, 190, 4 252 ; CHECK: br %r14 253 %shr = ashr i64 %foo, 60 254 store i64 %shr, i64 *%dest 255 %and = and i64 %shr, 14 256 ret i64 %and 257 } 258 259 ; Check that we use RISBG for shifted values even if the AND is a 260 ; natural zero extension. 261 define i64 @f23(i64 %foo) { 262 ; CHECK-LABEL: f23: 263 ; CHECK: risbg %r2, %r2, 56, 191, 62 264 ; CHECK: br %r14 265 %shr = lshr i64 %foo, 2 266 %and = and i64 %shr, 255 267 ret i64 %and 268 } 269 270 ; Test a case where the AND comes before a rotate. This needs a separate 271 ; mask and rotate. 272 define i32 @f24(i32 %foo) { 273 ; CHECK-LABEL: f24: 274 ; CHECK: nilf %r2, 254 275 ; CHECK: rll %r2, %r2, 29 276 ; CHECK: br %r14 277 %and = and i32 %foo, 254 278 %parta = lshr i32 %and, 3 279 %partb = shl i32 %and, 29 280 %rotl = or i32 %parta, %partb 281 ret i32 %rotl 282 } 283 284 ; ...and again with i64, where a single RISBG is enough. 285 define i64 @f25(i64 %foo) { 286 ; CHECK-LABEL: f25: 287 ; CHECK: risbg %r2, %r2, 57, 187, 3 288 ; CHECK: br %r14 289 %and = and i64 %foo, 14 290 %parta = shl i64 %and, 3 291 %partb = lshr i64 %and, 61 292 %rotl = or i64 %parta, %partb 293 ret i64 %rotl 294 } 295 296 ; Test a wrap-around case in which the AND comes before a rotate. 297 ; This again needs a separate mask and rotate. 298 define i32 @f26(i32 %foo) { 299 ; CHECK-LABEL: f26: 300 ; CHECK: rll %r2, %r2, 5 301 ; CHECK: br %r14 302 %and = and i32 %foo, -49 303 %parta = shl i32 %and, 5 304 %partb = lshr i32 %and, 27 305 %rotl = or i32 %parta, %partb 306 ret i32 %rotl 307 } 308 309 ; ...and again with i64, where a single RISBG is OK. 310 define i64 @f27(i64 %foo) { 311 ; CHECK-LABEL: f27: 312 ; CHECK: risbg %r2, %r2, 55, 180, 5 313 ; CHECK: br %r14 314 %and = and i64 %foo, -49 315 %parta = shl i64 %and, 5 316 %partb = lshr i64 %and, 59 317 %rotl = or i64 %parta, %partb 318 ret i64 %rotl 319 } 320 321 ; Test a case where the AND comes before a shift left. 322 define i32 @f28(i32 %foo) { 323 ; CHECK-LABEL: f28: 324 ; CHECK: risbg %r2, %r2, 32, 173, 17 325 ; CHECK: br %r14 326 %and = and i32 %foo, 32766 327 %shl = shl i32 %and, 17 328 ret i32 %shl 329 } 330 331 ; ...and again with i64. 332 define i64 @f29(i64 %foo) { 333 ; CHECK-LABEL: f29: 334 ; CHECK: risbg %r2, %r2, 0, 141, 49 335 ; CHECK: br %r14 336 %and = and i64 %foo, 32766 337 %shl = shl i64 %and, 49 338 ret i64 %shl 339 } 340 341 ; Test the next shift up from f28, in which the mask should get shortened. 342 define i32 @f30(i32 %foo) { 343 ; CHECK-LABEL: f30: 344 ; CHECK: risbg %r2, %r2, 32, 172, 18 345 ; CHECK: br %r14 346 %and = and i32 %foo, 32766 347 %shl = shl i32 %and, 18 348 ret i32 %shl 349 } 350 351 ; ...and again with i64. 352 define i64 @f31(i64 %foo) { 353 ; CHECK-LABEL: f31: 354 ; CHECK: risbg %r2, %r2, 0, 140, 50 355 ; CHECK: br %r14 356 %and = and i64 %foo, 32766 357 %shl = shl i64 %and, 50 358 ret i64 %shl 359 } 360 361 ; Test a wrap-around case in which the shift left comes after the AND. 362 ; We can't use RISBG for the shift in that case. 363 define i32 @f32(i32 %foo) { 364 ; CHECK-LABEL: f32: 365 ; CHECK: sll %r2 366 ; CHECK: br %r14 367 %and = and i32 %foo, -7 368 %shl = shl i32 %and, 10 369 ret i32 %shl 370 } 371 372 ; ...and again with i64. 373 define i64 @f33(i64 %foo) { 374 ; CHECK-LABEL: f33: 375 ; CHECK: sllg %r2 376 ; CHECK: br %r14 377 %and = and i64 %foo, -7 378 %shl = shl i64 %and, 10 379 ret i64 %shl 380 } 381 382 ; Test a case where the AND comes before a shift right. 383 define i32 @f34(i32 %foo) { 384 ; CHECK-LABEL: f34: 385 ; CHECK: risbg %r2, %r2, 57, 191, 55 386 ; CHECK: br %r14 387 %and = and i32 %foo, 65535 388 %shl = lshr i32 %and, 9 389 ret i32 %shl 390 } 391 392 ; ...and again with i64. 393 define i64 @f35(i64 %foo) { 394 ; CHECK-LABEL: f35: 395 ; CHECK: risbg %r2, %r2, 57, 191, 55 396 ; CHECK: br %r14 397 %and = and i64 %foo, 65535 398 %shl = lshr i64 %and, 9 399 ret i64 %shl 400 } 401 402 ; Test a wrap-around case where the AND comes before a shift right. 403 ; We can't use RISBG for the shift in that case. 404 define i32 @f36(i32 %foo) { 405 ; CHECK-LABEL: f36: 406 ; CHECK: srl %r2 407 ; CHECK: br %r14 408 %and = and i32 %foo, -25 409 %shl = lshr i32 %and, 1 410 ret i32 %shl 411 } 412 413 ; ...and again with i64. 414 define i64 @f37(i64 %foo) { 415 ; CHECK-LABEL: f37: 416 ; CHECK: srlg %r2 417 ; CHECK: br %r14 418 %and = and i64 %foo, -25 419 %shl = lshr i64 %and, 1 420 ret i64 %shl 421 } 422 423 ; Test a combination involving a large ASHR and a shift left. We can't 424 ; use RISBG there. 425 define i64 @f38(i64 %foo) { 426 ; CHECK-LABEL: f38: 427 ; CHECK: srag {{%r[0-5]}} 428 ; CHECK: sllg {{%r[0-5]}} 429 ; CHECK: br %r14 430 %ashr = ashr i64 %foo, 32 431 %shl = shl i64 %ashr, 5 432 ret i64 %shl 433 } 434 435 ; Try a similar thing in which no shifted sign bits are kept. 436 define i64 @f39(i64 %foo, i64 *%dest) { 437 ; CHECK-LABEL: f39: 438 ; CHECK: srag [[REG:%r[01345]]], %r2, 35 439 ; CHECK: risbg %r2, %r2, 33, 189, 31 440 ; CHECK: br %r14 441 %ashr = ashr i64 %foo, 35 442 store i64 %ashr, i64 *%dest 443 %shl = shl i64 %ashr, 2 444 %and = and i64 %shl, 2147483647 445 ret i64 %and 446 } 447 448 ; ...and again with the next highest shift value, where one sign bit is kept. 449 define i64 @f40(i64 %foo, i64 *%dest) { 450 ; CHECK-LABEL: f40: 451 ; CHECK: srag [[REG:%r[01345]]], %r2, 36 452 ; CHECK: risbg %r2, [[REG]], 33, 189, 2 453 ; CHECK: br %r14 454 %ashr = ashr i64 %foo, 36 455 store i64 %ashr, i64 *%dest 456 %shl = shl i64 %ashr, 2 457 %and = and i64 %shl, 2147483647 458 ret i64 %and 459 } 460 461 ; Check a case where the result is zero-extended. 462 define i64 @f41(i32 %a) { 463 ; CHECK-LABEL: f41 464 ; CHECK: risbg %r2, %r2, 36, 191, 62 465 ; CHECK: br %r14 466 %shl = shl i32 %a, 2 467 %shr = lshr i32 %shl, 4 468 %ext = zext i32 %shr to i64 469 ret i64 %ext 470 } 471 472 ; In this case the sign extension is converted to a pair of 32-bit shifts, 473 ; which is then extended to 64 bits. We previously used the wrong bit size 474 ; when testing whether the shifted-in bits of the shift right were significant. 475 define i64 @f42(i1 %x) { 476 ; CHECK-LABEL: f42: 477 ; CHECK: nilf %r2, 1 478 ; CHECK: lcr %r0, %r2 479 ; CHECK: llgcr %r2, %r0 480 ; CHECK: br %r14 481 %ext = sext i1 %x to i8 482 %ext2 = zext i8 %ext to i64 483 ret i64 %ext2 484 } 485 486 ; Check that we get the case where a 64-bit shift is used by a 32-bit and. 487 define signext i32 @f43(i64 %x) { 488 ; CHECK-LABEL: f43: 489 ; CHECK: risbg [[REG:%r[0-5]]], %r2, 32, 189, 52 490 ; CHECK: lgfr %r2, [[REG]] 491 %shr3 = lshr i64 %x, 12 492 %shr3.tr = trunc i64 %shr3 to i32 493 %conv = and i32 %shr3.tr, -4 494 ret i32 %conv 495 } 496 497 ; Check that we don't get the case where the 32-bit and mask is not contiguous 498 define signext i32 @f44(i64 %x) { 499 ; CHECK-LABEL: f44: 500 ; CHECK: srlg [[REG:%r[0-5]]], %r2, 12 501 %shr4 = lshr i64 %x, 12 502 %conv = trunc i64 %shr4 to i32 503 %and = and i32 %conv, 10 504 ret i32 %and 505 } 506
