1 ; Test vector intrinsics. 2 ; 3 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s 4 5 declare i32 @llvm.s390.lcbb(i8 *, i32) 6 declare <16 x i8> @llvm.s390.vlbb(i8 *, i32) 7 declare <16 x i8> @llvm.s390.vll(i32, i8 *) 8 declare <2 x i64> @llvm.s390.vpdi(<2 x i64>, <2 x i64>, i32) 9 declare <16 x i8> @llvm.s390.vperm(<16 x i8>, <16 x i8>, <16 x i8>) 10 declare <16 x i8> @llvm.s390.vpksh(<8 x i16>, <8 x i16>) 11 declare <8 x i16> @llvm.s390.vpksf(<4 x i32>, <4 x i32>) 12 declare <4 x i32> @llvm.s390.vpksg(<2 x i64>, <2 x i64>) 13 declare {<16 x i8>, i32} @llvm.s390.vpkshs(<8 x i16>, <8 x i16>) 14 declare {<8 x i16>, i32} @llvm.s390.vpksfs(<4 x i32>, <4 x i32>) 15 declare {<4 x i32>, i32} @llvm.s390.vpksgs(<2 x i64>, <2 x i64>) 16 declare <16 x i8> @llvm.s390.vpklsh(<8 x i16>, <8 x i16>) 17 declare <8 x i16> @llvm.s390.vpklsf(<4 x i32>, <4 x i32>) 18 declare <4 x i32> @llvm.s390.vpklsg(<2 x i64>, <2 x i64>) 19 declare {<16 x i8>, i32} @llvm.s390.vpklshs(<8 x i16>, <8 x i16>) 20 declare {<8 x i16>, i32} @llvm.s390.vpklsfs(<4 x i32>, <4 x i32>) 21 declare {<4 x i32>, i32} @llvm.s390.vpklsgs(<2 x i64>, <2 x i64>) 22 declare void @llvm.s390.vstl(<16 x i8>, i32, i8 *) 23 declare <8 x i16> @llvm.s390.vuphb(<16 x i8>) 24 declare <4 x i32> @llvm.s390.vuphh(<8 x i16>) 25 declare <2 x i64> @llvm.s390.vuphf(<4 x i32>) 26 declare <8 x i16> @llvm.s390.vuplhb(<16 x i8>) 27 declare <4 x i32> @llvm.s390.vuplhh(<8 x i16>) 28 declare <2 x i64> @llvm.s390.vuplhf(<4 x i32>) 29 declare <8 x i16> @llvm.s390.vuplb(<16 x i8>) 30 declare <4 x i32> @llvm.s390.vuplhw(<8 x i16>) 31 declare <2 x i64> @llvm.s390.vuplf(<4 x i32>) 32 declare <8 x i16> @llvm.s390.vupllb(<16 x i8>) 33 declare <4 x i32> @llvm.s390.vupllh(<8 x i16>) 34 declare <2 x i64> @llvm.s390.vupllf(<4 x i32>) 35 declare <16 x i8> @llvm.s390.vaccb(<16 x i8>, <16 x i8>) 36 declare <8 x i16> @llvm.s390.vacch(<8 x i16>, <8 x i16>) 37 declare <4 x i32> @llvm.s390.vaccf(<4 x i32>, <4 x i32>) 38 declare <2 x i64> @llvm.s390.vaccg(<2 x i64>, <2 x i64>) 39 declare <16 x i8> @llvm.s390.vaq(<16 x i8>, <16 x i8>) 40 declare <16 x i8> @llvm.s390.vacq(<16 x i8>, <16 x i8>, <16 x i8>) 41 declare <16 x i8> @llvm.s390.vaccq(<16 x i8>, <16 x i8>) 42 declare <16 x i8> @llvm.s390.vacccq(<16 x i8>, <16 x i8>, <16 x i8>) 43 declare <16 x i8> @llvm.s390.vavgb(<16 x i8>, <16 x i8>) 44 declare <8 x i16> @llvm.s390.vavgh(<8 x i16>, <8 x i16>) 45 declare <4 x i32> @llvm.s390.vavgf(<4 x i32>, <4 x i32>) 46 declare <2 x i64> @llvm.s390.vavgg(<2 x i64>, <2 x i64>) 47 declare <16 x i8> @llvm.s390.vavglb(<16 x i8>, <16 x i8>) 48 declare <8 x i16> @llvm.s390.vavglh(<8 x i16>, <8 x i16>) 49 declare <4 x i32> @llvm.s390.vavglf(<4 x i32>, <4 x i32>) 50 declare <2 x i64> @llvm.s390.vavglg(<2 x i64>, <2 x i64>) 51 declare <4 x i32> @llvm.s390.vcksm(<4 x i32>, <4 x i32>) 52 declare <8 x i16> @llvm.s390.vgfmb(<16 x i8>, <16 x i8>) 53 declare <4 x i32> @llvm.s390.vgfmh(<8 x i16>, <8 x i16>) 54 declare <2 x i64> @llvm.s390.vgfmf(<4 x i32>, <4 x i32>) 55 declare <16 x i8> @llvm.s390.vgfmg(<2 x i64>, <2 x i64>) 56 declare <8 x i16> @llvm.s390.vgfmab(<16 x i8>, <16 x i8>, <8 x i16>) 57 declare <4 x i32> @llvm.s390.vgfmah(<8 x i16>, <8 x i16>, <4 x i32>) 58 declare <2 x i64> @llvm.s390.vgfmaf(<4 x i32>, <4 x i32>, <2 x i64>) 59 declare <16 x i8> @llvm.s390.vgfmag(<2 x i64>, <2 x i64>, <16 x i8>) 60 declare <16 x i8> @llvm.s390.vmahb(<16 x i8>, <16 x i8>, <16 x i8>) 61 declare <8 x i16> @llvm.s390.vmahh(<8 x i16>, <8 x i16>, <8 x i16>) 62 declare <4 x i32> @llvm.s390.vmahf(<4 x i32>, <4 x i32>, <4 x i32>) 63 declare <16 x i8> @llvm.s390.vmalhb(<16 x i8>, <16 x i8>, <16 x i8>) 64 declare <8 x i16> @llvm.s390.vmalhh(<8 x i16>, <8 x i16>, <8 x i16>) 65 declare <4 x i32> @llvm.s390.vmalhf(<4 x i32>, <4 x i32>, <4 x i32>) 66 declare <8 x i16> @llvm.s390.vmaeb(<16 x i8>, <16 x i8>, <8 x i16>) 67 declare <4 x i32> @llvm.s390.vmaeh(<8 x i16>, <8 x i16>, <4 x i32>) 68 declare <2 x i64> @llvm.s390.vmaef(<4 x i32>, <4 x i32>, <2 x i64>) 69 declare <8 x i16> @llvm.s390.vmaleb(<16 x i8>, <16 x i8>, <8 x i16>) 70 declare <4 x i32> @llvm.s390.vmaleh(<8 x i16>, <8 x i16>, <4 x i32>) 71 declare <2 x i64> @llvm.s390.vmalef(<4 x i32>, <4 x i32>, <2 x i64>) 72 declare <8 x i16> @llvm.s390.vmaob(<16 x i8>, <16 x i8>, <8 x i16>) 73 declare <4 x i32> @llvm.s390.vmaoh(<8 x i16>, <8 x i16>, <4 x i32>) 74 declare <2 x i64> @llvm.s390.vmaof(<4 x i32>, <4 x i32>, <2 x i64>) 75 declare <8 x i16> @llvm.s390.vmalob(<16 x i8>, <16 x i8>, <8 x i16>) 76 declare <4 x i32> @llvm.s390.vmaloh(<8 x i16>, <8 x i16>, <4 x i32>) 77 declare <2 x i64> @llvm.s390.vmalof(<4 x i32>, <4 x i32>, <2 x i64>) 78 declare <16 x i8> @llvm.s390.vmhb(<16 x i8>, <16 x i8>) 79 declare <8 x i16> @llvm.s390.vmhh(<8 x i16>, <8 x i16>) 80 declare <4 x i32> @llvm.s390.vmhf(<4 x i32>, <4 x i32>) 81 declare <16 x i8> @llvm.s390.vmlhb(<16 x i8>, <16 x i8>) 82 declare <8 x i16> @llvm.s390.vmlhh(<8 x i16>, <8 x i16>) 83 declare <4 x i32> @llvm.s390.vmlhf(<4 x i32>, <4 x i32>) 84 declare <8 x i16> @llvm.s390.vmeb(<16 x i8>, <16 x i8>) 85 declare <4 x i32> @llvm.s390.vmeh(<8 x i16>, <8 x i16>) 86 declare <2 x i64> @llvm.s390.vmef(<4 x i32>, <4 x i32>) 87 declare <8 x i16> @llvm.s390.vmleb(<16 x i8>, <16 x i8>) 88 declare <4 x i32> @llvm.s390.vmleh(<8 x i16>, <8 x i16>) 89 declare <2 x i64> @llvm.s390.vmlef(<4 x i32>, <4 x i32>) 90 declare <8 x i16> @llvm.s390.vmob(<16 x i8>, <16 x i8>) 91 declare <4 x i32> @llvm.s390.vmoh(<8 x i16>, <8 x i16>) 92 declare <2 x i64> @llvm.s390.vmof(<4 x i32>, <4 x i32>) 93 declare <8 x i16> @llvm.s390.vmlob(<16 x i8>, <16 x i8>) 94 declare <4 x i32> @llvm.s390.vmloh(<8 x i16>, <8 x i16>) 95 declare <2 x i64> @llvm.s390.vmlof(<4 x i32>, <4 x i32>) 96 declare <16 x i8> @llvm.s390.verllvb(<16 x i8>, <16 x i8>) 97 declare <8 x i16> @llvm.s390.verllvh(<8 x i16>, <8 x i16>) 98 declare <4 x i32> @llvm.s390.verllvf(<4 x i32>, <4 x i32>) 99 declare <2 x i64> @llvm.s390.verllvg(<2 x i64>, <2 x i64>) 100 declare <16 x i8> @llvm.s390.verllb(<16 x i8>, i32) 101 declare <8 x i16> @llvm.s390.verllh(<8 x i16>, i32) 102 declare <4 x i32> @llvm.s390.verllf(<4 x i32>, i32) 103 declare <2 x i64> @llvm.s390.verllg(<2 x i64>, i32) 104 declare <16 x i8> @llvm.s390.verimb(<16 x i8>, <16 x i8>, <16 x i8>, i32) 105 declare <8 x i16> @llvm.s390.verimh(<8 x i16>, <8 x i16>, <8 x i16>, i32) 106 declare <4 x i32> @llvm.s390.verimf(<4 x i32>, <4 x i32>, <4 x i32>, i32) 107 declare <2 x i64> @llvm.s390.verimg(<2 x i64>, <2 x i64>, <2 x i64>, i32) 108 declare <16 x i8> @llvm.s390.vsl(<16 x i8>, <16 x i8>) 109 declare <16 x i8> @llvm.s390.vslb(<16 x i8>, <16 x i8>) 110 declare <16 x i8> @llvm.s390.vsra(<16 x i8>, <16 x i8>) 111 declare <16 x i8> @llvm.s390.vsrab(<16 x i8>, <16 x i8>) 112 declare <16 x i8> @llvm.s390.vsrl(<16 x i8>, <16 x i8>) 113 declare <16 x i8> @llvm.s390.vsrlb(<16 x i8>, <16 x i8>) 114 declare <16 x i8> @llvm.s390.vsldb(<16 x i8>, <16 x i8>, i32) 115 declare <16 x i8> @llvm.s390.vscbib(<16 x i8>, <16 x i8>) 116 declare <8 x i16> @llvm.s390.vscbih(<8 x i16>, <8 x i16>) 117 declare <4 x i32> @llvm.s390.vscbif(<4 x i32>, <4 x i32>) 118 declare <2 x i64> @llvm.s390.vscbig(<2 x i64>, <2 x i64>) 119 declare <16 x i8> @llvm.s390.vsq(<16 x i8>, <16 x i8>) 120 declare <16 x i8> @llvm.s390.vsbiq(<16 x i8>, <16 x i8>, <16 x i8>) 121 declare <16 x i8> @llvm.s390.vscbiq(<16 x i8>, <16 x i8>) 122 declare <16 x i8> @llvm.s390.vsbcbiq(<16 x i8>, <16 x i8>, <16 x i8>) 123 declare <4 x i32> @llvm.s390.vsumb(<16 x i8>, <16 x i8>) 124 declare <4 x i32> @llvm.s390.vsumh(<8 x i16>, <8 x i16>) 125 declare <2 x i64> @llvm.s390.vsumgh(<8 x i16>, <8 x i16>) 126 declare <2 x i64> @llvm.s390.vsumgf(<4 x i32>, <4 x i32>) 127 declare <16 x i8> @llvm.s390.vsumqf(<4 x i32>, <4 x i32>) 128 declare <16 x i8> @llvm.s390.vsumqg(<2 x i64>, <2 x i64>) 129 declare i32 @llvm.s390.vtm(<16 x i8>, <16 x i8>) 130 declare {<16 x i8>, i32} @llvm.s390.vceqbs(<16 x i8>, <16 x i8>) 131 declare {<8 x i16>, i32} @llvm.s390.vceqhs(<8 x i16>, <8 x i16>) 132 declare {<4 x i32>, i32} @llvm.s390.vceqfs(<4 x i32>, <4 x i32>) 133 declare {<2 x i64>, i32} @llvm.s390.vceqgs(<2 x i64>, <2 x i64>) 134 declare {<16 x i8>, i32} @llvm.s390.vchbs(<16 x i8>, <16 x i8>) 135 declare {<8 x i16>, i32} @llvm.s390.vchhs(<8 x i16>, <8 x i16>) 136 declare {<4 x i32>, i32} @llvm.s390.vchfs(<4 x i32>, <4 x i32>) 137 declare {<2 x i64>, i32} @llvm.s390.vchgs(<2 x i64>, <2 x i64>) 138 declare {<16 x i8>, i32} @llvm.s390.vchlbs(<16 x i8>, <16 x i8>) 139 declare {<8 x i16>, i32} @llvm.s390.vchlhs(<8 x i16>, <8 x i16>) 140 declare {<4 x i32>, i32} @llvm.s390.vchlfs(<4 x i32>, <4 x i32>) 141 declare {<2 x i64>, i32} @llvm.s390.vchlgs(<2 x i64>, <2 x i64>) 142 declare <16 x i8> @llvm.s390.vfaeb(<16 x i8>, <16 x i8>, i32) 143 declare <8 x i16> @llvm.s390.vfaeh(<8 x i16>, <8 x i16>, i32) 144 declare <4 x i32> @llvm.s390.vfaef(<4 x i32>, <4 x i32>, i32) 145 declare {<16 x i8>, i32} @llvm.s390.vfaebs(<16 x i8>, <16 x i8>, i32) 146 declare {<8 x i16>, i32} @llvm.s390.vfaehs(<8 x i16>, <8 x i16>, i32) 147 declare {<4 x i32>, i32} @llvm.s390.vfaefs(<4 x i32>, <4 x i32>, i32) 148 declare <16 x i8> @llvm.s390.vfaezb(<16 x i8>, <16 x i8>, i32) 149 declare <8 x i16> @llvm.s390.vfaezh(<8 x i16>, <8 x i16>, i32) 150 declare <4 x i32> @llvm.s390.vfaezf(<4 x i32>, <4 x i32>, i32) 151 declare {<16 x i8>, i32} @llvm.s390.vfaezbs(<16 x i8>, <16 x i8>, i32) 152 declare {<8 x i16>, i32} @llvm.s390.vfaezhs(<8 x i16>, <8 x i16>, i32) 153 declare {<4 x i32>, i32} @llvm.s390.vfaezfs(<4 x i32>, <4 x i32>, i32) 154 declare <16 x i8> @llvm.s390.vfeeb(<16 x i8>, <16 x i8>) 155 declare <8 x i16> @llvm.s390.vfeeh(<8 x i16>, <8 x i16>) 156 declare <4 x i32> @llvm.s390.vfeef(<4 x i32>, <4 x i32>) 157 declare {<16 x i8>, i32} @llvm.s390.vfeebs(<16 x i8>, <16 x i8>) 158 declare {<8 x i16>, i32} @llvm.s390.vfeehs(<8 x i16>, <8 x i16>) 159 declare {<4 x i32>, i32} @llvm.s390.vfeefs(<4 x i32>, <4 x i32>) 160 declare <16 x i8> @llvm.s390.vfeezb(<16 x i8>, <16 x i8>) 161 declare <8 x i16> @llvm.s390.vfeezh(<8 x i16>, <8 x i16>) 162 declare <4 x i32> @llvm.s390.vfeezf(<4 x i32>, <4 x i32>) 163 declare {<16 x i8>, i32} @llvm.s390.vfeezbs(<16 x i8>, <16 x i8>) 164 declare {<8 x i16>, i32} @llvm.s390.vfeezhs(<8 x i16>, <8 x i16>) 165 declare {<4 x i32>, i32} @llvm.s390.vfeezfs(<4 x i32>, <4 x i32>) 166 declare <16 x i8> @llvm.s390.vfeneb(<16 x i8>, <16 x i8>) 167 declare <8 x i16> @llvm.s390.vfeneh(<8 x i16>, <8 x i16>) 168 declare <4 x i32> @llvm.s390.vfenef(<4 x i32>, <4 x i32>) 169 declare {<16 x i8>, i32} @llvm.s390.vfenebs(<16 x i8>, <16 x i8>) 170 declare {<8 x i16>, i32} @llvm.s390.vfenehs(<8 x i16>, <8 x i16>) 171 declare {<4 x i32>, i32} @llvm.s390.vfenefs(<4 x i32>, <4 x i32>) 172 declare <16 x i8> @llvm.s390.vfenezb(<16 x i8>, <16 x i8>) 173 declare <8 x i16> @llvm.s390.vfenezh(<8 x i16>, <8 x i16>) 174 declare <4 x i32> @llvm.s390.vfenezf(<4 x i32>, <4 x i32>) 175 declare {<16 x i8>, i32} @llvm.s390.vfenezbs(<16 x i8>, <16 x i8>) 176 declare {<8 x i16>, i32} @llvm.s390.vfenezhs(<8 x i16>, <8 x i16>) 177 declare {<4 x i32>, i32} @llvm.s390.vfenezfs(<4 x i32>, <4 x i32>) 178 declare <16 x i8> @llvm.s390.vistrb(<16 x i8>) 179 declare <8 x i16> @llvm.s390.vistrh(<8 x i16>) 180 declare <4 x i32> @llvm.s390.vistrf(<4 x i32>) 181 declare {<16 x i8>, i32} @llvm.s390.vistrbs(<16 x i8>) 182 declare {<8 x i16>, i32} @llvm.s390.vistrhs(<8 x i16>) 183 declare {<4 x i32>, i32} @llvm.s390.vistrfs(<4 x i32>) 184 declare <16 x i8> @llvm.s390.vstrcb(<16 x i8>, <16 x i8>, <16 x i8>, i32) 185 declare <8 x i16> @llvm.s390.vstrch(<8 x i16>, <8 x i16>, <8 x i16>, i32) 186 declare <4 x i32> @llvm.s390.vstrcf(<4 x i32>, <4 x i32>, <4 x i32>, i32) 187 declare {<16 x i8>, i32} @llvm.s390.vstrcbs(<16 x i8>, <16 x i8>, <16 x i8>, 188 i32) 189 declare {<8 x i16>, i32} @llvm.s390.vstrchs(<8 x i16>, <8 x i16>, <8 x i16>, 190 i32) 191 declare {<4 x i32>, i32} @llvm.s390.vstrcfs(<4 x i32>, <4 x i32>, <4 x i32>, 192 i32) 193 declare <16 x i8> @llvm.s390.vstrczb(<16 x i8>, <16 x i8>, <16 x i8>, i32) 194 declare <8 x i16> @llvm.s390.vstrczh(<8 x i16>, <8 x i16>, <8 x i16>, i32) 195 declare <4 x i32> @llvm.s390.vstrczf(<4 x i32>, <4 x i32>, <4 x i32>, i32) 196 declare {<16 x i8>, i32} @llvm.s390.vstrczbs(<16 x i8>, <16 x i8>, <16 x i8>, 197 i32) 198 declare {<8 x i16>, i32} @llvm.s390.vstrczhs(<8 x i16>, <8 x i16>, <8 x i16>, 199 i32) 200 declare {<4 x i32>, i32} @llvm.s390.vstrczfs(<4 x i32>, <4 x i32>, <4 x i32>, 201 i32) 202 declare {<2 x i64>, i32} @llvm.s390.vfcedbs(<2 x double>, <2 x double>) 203 declare {<2 x i64>, i32} @llvm.s390.vfchdbs(<2 x double>, <2 x double>) 204 declare {<2 x i64>, i32} @llvm.s390.vfchedbs(<2 x double>, <2 x double>) 205 declare {<2 x i64>, i32} @llvm.s390.vftcidb(<2 x double>, i32) 206 declare <2 x double> @llvm.s390.vfidb(<2 x double>, i32, i32) 207 208 ; LCBB with the lowest M3 operand. 209 define i32 @test_lcbb1(i8 *%ptr) { 210 ; CHECK-LABEL: test_lcbb1: 211 ; CHECK: lcbb %r2, 0(%r2), 0 212 ; CHECK: br %r14 213 %res = call i32 @llvm.s390.lcbb(i8 *%ptr, i32 0) 214 ret i32 %res 215 } 216 217 ; LCBB with the highest M3 operand. 218 define i32 @test_lcbb2(i8 *%ptr) { 219 ; CHECK-LABEL: test_lcbb2: 220 ; CHECK: lcbb %r2, 0(%r2), 15 221 ; CHECK: br %r14 222 %res = call i32 @llvm.s390.lcbb(i8 *%ptr, i32 15) 223 ret i32 %res 224 } 225 226 ; LCBB with a displacement and index. 227 define i32 @test_lcbb3(i8 *%base, i64 %index) { 228 ; CHECK-LABEL: test_lcbb3: 229 ; CHECK: lcbb %r2, 4095({{%r2,%r3|%r3,%r2}}), 4 230 ; CHECK: br %r14 231 %add = add i64 %index, 4095 232 %ptr = getelementptr i8, i8 *%base, i64 %add 233 %res = call i32 @llvm.s390.lcbb(i8 *%ptr, i32 4) 234 ret i32 %res 235 } 236 237 ; LCBB with an out-of-range displacement. 238 define i32 @test_lcbb4(i8 *%base) { 239 ; CHECK-LABEL: test_lcbb4: 240 ; CHECK: lcbb %r2, 0({{%r[1-5]}}), 5 241 ; CHECK: br %r14 242 %ptr = getelementptr i8, i8 *%base, i64 4096 243 %res = call i32 @llvm.s390.lcbb(i8 *%ptr, i32 5) 244 ret i32 %res 245 } 246 247 ; VLBB with the lowest M3 operand. 248 define <16 x i8> @test_vlbb1(i8 *%ptr) { 249 ; CHECK-LABEL: test_vlbb1: 250 ; CHECK: vlbb %v24, 0(%r2), 0 251 ; CHECK: br %r14 252 %res = call <16 x i8> @llvm.s390.vlbb(i8 *%ptr, i32 0) 253 ret <16 x i8> %res 254 } 255 256 ; VLBB with the highest M3 operand. 257 define <16 x i8> @test_vlbb2(i8 *%ptr) { 258 ; CHECK-LABEL: test_vlbb2: 259 ; CHECK: vlbb %v24, 0(%r2), 15 260 ; CHECK: br %r14 261 %res = call <16 x i8> @llvm.s390.vlbb(i8 *%ptr, i32 15) 262 ret <16 x i8> %res 263 } 264 265 ; VLBB with a displacement and index. 266 define <16 x i8> @test_vlbb3(i8 *%base, i64 %index) { 267 ; CHECK-LABEL: test_vlbb3: 268 ; CHECK: vlbb %v24, 4095({{%r2,%r3|%r3,%r2}}), 4 269 ; CHECK: br %r14 270 %add = add i64 %index, 4095 271 %ptr = getelementptr i8, i8 *%base, i64 %add 272 %res = call <16 x i8> @llvm.s390.vlbb(i8 *%ptr, i32 4) 273 ret <16 x i8> %res 274 } 275 276 ; VLBB with an out-of-range displacement. 277 define <16 x i8> @test_vlbb4(i8 *%base) { 278 ; CHECK-LABEL: test_vlbb4: 279 ; CHECK: vlbb %v24, 0({{%r[1-5]}}), 5 280 ; CHECK: br %r14 281 %ptr = getelementptr i8, i8 *%base, i64 4096 282 %res = call <16 x i8> @llvm.s390.vlbb(i8 *%ptr, i32 5) 283 ret <16 x i8> %res 284 } 285 286 ; VLL with the lowest in-range displacement. 287 define <16 x i8> @test_vll1(i8 *%ptr, i32 %length) { 288 ; CHECK-LABEL: test_vll1: 289 ; CHECK: vll %v24, %r3, 0(%r2) 290 ; CHECK: br %r14 291 %res = call <16 x i8> @llvm.s390.vll(i32 %length, i8 *%ptr) 292 ret <16 x i8> %res 293 } 294 295 ; VLL with the highest in-range displacement. 296 define <16 x i8> @test_vll2(i8 *%base, i32 %length) { 297 ; CHECK-LABEL: test_vll2: 298 ; CHECK: vll %v24, %r3, 4095(%r2) 299 ; CHECK: br %r14 300 %ptr = getelementptr i8, i8 *%base, i64 4095 301 %res = call <16 x i8> @llvm.s390.vll(i32 %length, i8 *%ptr) 302 ret <16 x i8> %res 303 } 304 305 ; VLL with an out-of-range displacementa. 306 define <16 x i8> @test_vll3(i8 *%base, i32 %length) { 307 ; CHECK-LABEL: test_vll3: 308 ; CHECK: vll %v24, %r3, 0({{%r[1-5]}}) 309 ; CHECK: br %r14 310 %ptr = getelementptr i8, i8 *%base, i64 4096 311 %res = call <16 x i8> @llvm.s390.vll(i32 %length, i8 *%ptr) 312 ret <16 x i8> %res 313 } 314 315 ; Check that VLL doesn't allow an index. 316 define <16 x i8> @test_vll4(i8 *%base, i64 %index, i32 %length) { 317 ; CHECK-LABEL: test_vll4: 318 ; CHECK: vll %v24, %r4, 0({{%r[1-5]}}) 319 ; CHECK: br %r14 320 %ptr = getelementptr i8, i8 *%base, i64 %index 321 %res = call <16 x i8> @llvm.s390.vll(i32 %length, i8 *%ptr) 322 ret <16 x i8> %res 323 } 324 325 ; VPDI taking element 0 from each half. 326 define <2 x i64> @test_vpdi1(<2 x i64> %a, <2 x i64> %b) { 327 ; CHECK-LABEL: test_vpdi1: 328 ; CHECK: vpdi %v24, %v24, %v26, 0 329 ; CHECK: br %r14 330 %res = call <2 x i64> @llvm.s390.vpdi(<2 x i64> %a, <2 x i64> %b, i32 0) 331 ret <2 x i64> %res 332 } 333 334 ; VPDI taking element 1 from each half. 335 define <2 x i64> @test_vpdi2(<2 x i64> %a, <2 x i64> %b) { 336 ; CHECK-LABEL: test_vpdi2: 337 ; CHECK: vpdi %v24, %v24, %v26, 5 338 ; CHECK: br %r14 339 %res = call <2 x i64> @llvm.s390.vpdi(<2 x i64> %a, <2 x i64> %b, i32 5) 340 ret <2 x i64> %res 341 } 342 343 ; VPERM. 344 define <16 x i8> @test_vperm(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) { 345 ; CHECK-LABEL: test_vperm: 346 ; CHECK: vperm %v24, %v24, %v26, %v28 347 ; CHECK: br %r14 348 %res = call <16 x i8> @llvm.s390.vperm(<16 x i8> %a, <16 x i8> %b, 349 <16 x i8> %c) 350 ret <16 x i8> %res 351 } 352 353 ; VPKSH. 354 define <16 x i8> @test_vpksh(<8 x i16> %a, <8 x i16> %b) { 355 ; CHECK-LABEL: test_vpksh: 356 ; CHECK: vpksh %v24, %v24, %v26 357 ; CHECK: br %r14 358 %res = call <16 x i8> @llvm.s390.vpksh(<8 x i16> %a, <8 x i16> %b) 359 ret <16 x i8> %res 360 } 361 362 ; VPKSF. 363 define <8 x i16> @test_vpksf(<4 x i32> %a, <4 x i32> %b) { 364 ; CHECK-LABEL: test_vpksf: 365 ; CHECK: vpksf %v24, %v24, %v26 366 ; CHECK: br %r14 367 %res = call <8 x i16> @llvm.s390.vpksf(<4 x i32> %a, <4 x i32> %b) 368 ret <8 x i16> %res 369 } 370 371 ; VPKSG. 372 define <4 x i32> @test_vpksg(<2 x i64> %a, <2 x i64> %b) { 373 ; CHECK-LABEL: test_vpksg: 374 ; CHECK: vpksg %v24, %v24, %v26 375 ; CHECK: br %r14 376 %res = call <4 x i32> @llvm.s390.vpksg(<2 x i64> %a, <2 x i64> %b) 377 ret <4 x i32> %res 378 } 379 380 ; VPKSHS with no processing of the result. 381 define <16 x i8> @test_vpkshs(<8 x i16> %a, <8 x i16> %b, i32 *%ccptr) { 382 ; CHECK-LABEL: test_vpkshs: 383 ; CHECK: vpkshs %v24, %v24, %v26 384 ; CHECK: ipm [[REG:%r[0-5]]] 385 ; CHECK: srl [[REG]], 28 386 ; CHECK: st [[REG]], 0(%r2) 387 ; CHECK: br %r14 388 %call = call {<16 x i8>, i32} @llvm.s390.vpkshs(<8 x i16> %a, <8 x i16> %b) 389 %res = extractvalue {<16 x i8>, i32} %call, 0 390 %cc = extractvalue {<16 x i8>, i32} %call, 1 391 store i32 %cc, i32 *%ccptr 392 ret <16 x i8> %res 393 } 394 395 ; VPKSHS, storing to %ptr if all values were saturated. 396 define <16 x i8> @test_vpkshs_all_store(<8 x i16> %a, <8 x i16> %b, i32 *%ptr) { 397 ; CHECK-LABEL: test_vpkshs_all_store: 398 ; CHECK: vpkshs %v24, %v24, %v26 399 ; CHECK-NEXT: {{bnor|bler}} %r14 400 ; CHECK: mvhi 0(%r2), 0 401 ; CHECK: br %r14 402 %call = call {<16 x i8>, i32} @llvm.s390.vpkshs(<8 x i16> %a, <8 x i16> %b) 403 %res = extractvalue {<16 x i8>, i32} %call, 0 404 %cc = extractvalue {<16 x i8>, i32} %call, 1 405 %cmp = icmp uge i32 %cc, 3 406 br i1 %cmp, label %store, label %exit 407 408 store: 409 store i32 0, i32 *%ptr 410 br label %exit 411 412 exit: 413 ret <16 x i8> %res 414 } 415 416 ; VPKSFS with no processing of the result. 417 define <8 x i16> @test_vpksfs(<4 x i32> %a, <4 x i32> %b, i32 *%ccptr) { 418 ; CHECK-LABEL: test_vpksfs: 419 ; CHECK: vpksfs %v24, %v24, %v26 420 ; CHECK: ipm [[REG:%r[0-5]]] 421 ; CHECK: srl [[REG]], 28 422 ; CHECK: st [[REG]], 0(%r2) 423 ; CHECK: br %r14 424 %call = call {<8 x i16>, i32} @llvm.s390.vpksfs(<4 x i32> %a, <4 x i32> %b) 425 %res = extractvalue {<8 x i16>, i32} %call, 0 426 %cc = extractvalue {<8 x i16>, i32} %call, 1 427 store i32 %cc, i32 *%ccptr 428 ret <8 x i16> %res 429 } 430 431 ; VPKSFS, storing to %ptr if any values were saturated. 432 define <8 x i16> @test_vpksfs_any_store(<4 x i32> %a, <4 x i32> %b, i32 *%ptr) { 433 ; CHECK-LABEL: test_vpksfs_any_store: 434 ; CHECK: vpksfs %v24, %v24, %v26 435 ; CHECK-NEXT: {{bher|ber}} %r14 436 ; CHECK: mvhi 0(%r2), 0 437 ; CHECK: br %r14 438 %call = call {<8 x i16>, i32} @llvm.s390.vpksfs(<4 x i32> %a, <4 x i32> %b) 439 %res = extractvalue {<8 x i16>, i32} %call, 0 440 %cc = extractvalue {<8 x i16>, i32} %call, 1 441 %cmp = icmp ugt i32 %cc, 0 442 br i1 %cmp, label %store, label %exit 443 444 store: 445 store i32 0, i32 *%ptr 446 br label %exit 447 448 exit: 449 ret <8 x i16> %res 450 } 451 452 ; VPKSGS with no processing of the result. 453 define <4 x i32> @test_vpksgs(<2 x i64> %a, <2 x i64> %b, i32 *%ccptr) { 454 ; CHECK-LABEL: test_vpksgs: 455 ; CHECK: vpksgs %v24, %v24, %v26 456 ; CHECK: ipm [[REG:%r[0-5]]] 457 ; CHECK: srl [[REG]], 28 458 ; CHECK: st [[REG]], 0(%r2) 459 ; CHECK: br %r14 460 %call = call {<4 x i32>, i32} @llvm.s390.vpksgs(<2 x i64> %a, <2 x i64> %b) 461 %res = extractvalue {<4 x i32>, i32} %call, 0 462 %cc = extractvalue {<4 x i32>, i32} %call, 1 463 store i32 %cc, i32 *%ccptr 464 ret <4 x i32> %res 465 } 466 467 ; VPKSGS, storing to %ptr if no elements were saturated 468 define <4 x i32> @test_vpksgs_none_store(<2 x i64> %a, <2 x i64> %b, 469 i32 *%ptr) { 470 ; CHECK-LABEL: test_vpksgs_none_store: 471 ; CHECK: vpksgs %v24, %v24, %v26 472 ; CHECK-NEXT: {{bnher|bner}} %r14 473 ; CHECK: mvhi 0(%r2), 0 474 ; CHECK: br %r14 475 %call = call {<4 x i32>, i32} @llvm.s390.vpksgs(<2 x i64> %a, <2 x i64> %b) 476 %res = extractvalue {<4 x i32>, i32} %call, 0 477 %cc = extractvalue {<4 x i32>, i32} %call, 1 478 %cmp = icmp sle i32 %cc, 0 479 br i1 %cmp, label %store, label %exit 480 481 store: 482 store i32 0, i32 *%ptr 483 br label %exit 484 485 exit: 486 ret <4 x i32> %res 487 } 488 489 ; VPKLSH. 490 define <16 x i8> @test_vpklsh(<8 x i16> %a, <8 x i16> %b) { 491 ; CHECK-LABEL: test_vpklsh: 492 ; CHECK: vpklsh %v24, %v24, %v26 493 ; CHECK: br %r14 494 %res = call <16 x i8> @llvm.s390.vpklsh(<8 x i16> %a, <8 x i16> %b) 495 ret <16 x i8> %res 496 } 497 498 ; VPKLSF. 499 define <8 x i16> @test_vpklsf(<4 x i32> %a, <4 x i32> %b) { 500 ; CHECK-LABEL: test_vpklsf: 501 ; CHECK: vpklsf %v24, %v24, %v26 502 ; CHECK: br %r14 503 %res = call <8 x i16> @llvm.s390.vpklsf(<4 x i32> %a, <4 x i32> %b) 504 ret <8 x i16> %res 505 } 506 507 ; VPKLSG. 508 define <4 x i32> @test_vpklsg(<2 x i64> %a, <2 x i64> %b) { 509 ; CHECK-LABEL: test_vpklsg: 510 ; CHECK: vpklsg %v24, %v24, %v26 511 ; CHECK: br %r14 512 %res = call <4 x i32> @llvm.s390.vpklsg(<2 x i64> %a, <2 x i64> %b) 513 ret <4 x i32> %res 514 } 515 516 ; VPKLSHS with no processing of the result. 517 define <16 x i8> @test_vpklshs(<8 x i16> %a, <8 x i16> %b, i32 *%ccptr) { 518 ; CHECK-LABEL: test_vpklshs: 519 ; CHECK: vpklshs %v24, %v24, %v26 520 ; CHECK: ipm [[REG:%r[0-5]]] 521 ; CHECK: srl [[REG]], 28 522 ; CHECK: st [[REG]], 0(%r2) 523 ; CHECK: br %r14 524 %call = call {<16 x i8>, i32} @llvm.s390.vpklshs(<8 x i16> %a, <8 x i16> %b) 525 %res = extractvalue {<16 x i8>, i32} %call, 0 526 %cc = extractvalue {<16 x i8>, i32} %call, 1 527 store i32 %cc, i32 *%ccptr 528 ret <16 x i8> %res 529 } 530 531 ; VPKLSHS, storing to %ptr if all values were saturated. 532 define <16 x i8> @test_vpklshs_all_store(<8 x i16> %a, <8 x i16> %b, 533 i32 *%ptr) { 534 ; CHECK-LABEL: test_vpklshs_all_store: 535 ; CHECK: vpklshs %v24, %v24, %v26 536 ; CHECK-NEXT: {{bnor|bler}} %r14 537 ; CHECK: mvhi 0(%r2), 0 538 ; CHECK: br %r14 539 %call = call {<16 x i8>, i32} @llvm.s390.vpklshs(<8 x i16> %a, <8 x i16> %b) 540 %res = extractvalue {<16 x i8>, i32} %call, 0 541 %cc = extractvalue {<16 x i8>, i32} %call, 1 542 %cmp = icmp eq i32 %cc, 3 543 br i1 %cmp, label %store, label %exit 544 545 store: 546 store i32 0, i32 *%ptr 547 br label %exit 548 549 exit: 550 ret <16 x i8> %res 551 } 552 553 ; VPKLSFS with no processing of the result. 554 define <8 x i16> @test_vpklsfs(<4 x i32> %a, <4 x i32> %b, i32 *%ccptr) { 555 ; CHECK-LABEL: test_vpklsfs: 556 ; CHECK: vpklsfs %v24, %v24, %v26 557 ; CHECK: ipm [[REG:%r[0-5]]] 558 ; CHECK: srl [[REG]], 28 559 ; CHECK: st [[REG]], 0(%r2) 560 ; CHECK: br %r14 561 %call = call {<8 x i16>, i32} @llvm.s390.vpklsfs(<4 x i32> %a, <4 x i32> %b) 562 %res = extractvalue {<8 x i16>, i32} %call, 0 563 %cc = extractvalue {<8 x i16>, i32} %call, 1 564 store i32 %cc, i32 *%ccptr 565 ret <8 x i16> %res 566 } 567 568 ; VPKLSFS, storing to %ptr if any values were saturated. 569 define <8 x i16> @test_vpklsfs_any_store(<4 x i32> %a, <4 x i32> %b, 570 i32 *%ptr) { 571 ; CHECK-LABEL: test_vpklsfs_any_store: 572 ; CHECK: vpklsfs %v24, %v24, %v26 573 ; CHECK-NEXT: {{bher|ber}} %r14 574 ; CHECK: mvhi 0(%r2), 0 575 ; CHECK: br %r14 576 %call = call {<8 x i16>, i32} @llvm.s390.vpklsfs(<4 x i32> %a, <4 x i32> %b) 577 %res = extractvalue {<8 x i16>, i32} %call, 0 578 %cc = extractvalue {<8 x i16>, i32} %call, 1 579 %cmp = icmp ne i32 %cc, 0 580 br i1 %cmp, label %store, label %exit 581 582 store: 583 store i32 0, i32 *%ptr 584 br label %exit 585 586 exit: 587 ret <8 x i16> %res 588 } 589 590 ; VPKLSGS with no processing of the result. 591 define <4 x i32> @test_vpklsgs(<2 x i64> %a, <2 x i64> %b, i32 *%ccptr) { 592 ; CHECK-LABEL: test_vpklsgs: 593 ; CHECK: vpklsgs %v24, %v24, %v26 594 ; CHECK: ipm [[REG:%r[0-5]]] 595 ; CHECK: srl [[REG]], 28 596 ; CHECK: st [[REG]], 0(%r2) 597 ; CHECK: br %r14 598 %call = call {<4 x i32>, i32} @llvm.s390.vpklsgs(<2 x i64> %a, <2 x i64> %b) 599 %res = extractvalue {<4 x i32>, i32} %call, 0 600 %cc = extractvalue {<4 x i32>, i32} %call, 1 601 store i32 %cc, i32 *%ccptr 602 ret <4 x i32> %res 603 } 604 605 ; VPKLSGS, storing to %ptr if no elements were saturated 606 define <4 x i32> @test_vpklsgs_none_store(<2 x i64> %a, <2 x i64> %b, 607 i32 *%ptr) { 608 ; CHECK-LABEL: test_vpklsgs_none_store: 609 ; CHECK: vpklsgs %v24, %v24, %v26 610 ; CHECK-NEXT: {{bnher|bner}} %r14 611 ; CHECK: mvhi 0(%r2), 0 612 ; CHECK: br %r14 613 %call = call {<4 x i32>, i32} @llvm.s390.vpklsgs(<2 x i64> %a, <2 x i64> %b) 614 %res = extractvalue {<4 x i32>, i32} %call, 0 615 %cc = extractvalue {<4 x i32>, i32} %call, 1 616 %cmp = icmp eq i32 %cc, 0 617 br i1 %cmp, label %store, label %exit 618 619 store: 620 store i32 0, i32 *%ptr 621 br label %exit 622 623 exit: 624 ret <4 x i32> %res 625 } 626 627 ; VSTL with the lowest in-range displacement. 628 define void @test_vstl1(<16 x i8> %vec, i8 *%ptr, i32 %length) { 629 ; CHECK-LABEL: test_vstl1: 630 ; CHECK: vstl %v24, %r3, 0(%r2) 631 ; CHECK: br %r14 632 call void @llvm.s390.vstl(<16 x i8> %vec, i32 %length, i8 *%ptr) 633 ret void 634 } 635 636 ; VSTL with the highest in-range displacement. 637 define void @test_vstl2(<16 x i8> %vec, i8 *%base, i32 %length) { 638 ; CHECK-LABEL: test_vstl2: 639 ; CHECK: vstl %v24, %r3, 4095(%r2) 640 ; CHECK: br %r14 641 %ptr = getelementptr i8, i8 *%base, i64 4095 642 call void @llvm.s390.vstl(<16 x i8> %vec, i32 %length, i8 *%ptr) 643 ret void 644 } 645 646 ; VSTL with an out-of-range displacement. 647 define void @test_vstl3(<16 x i8> %vec, i8 *%base, i32 %length) { 648 ; CHECK-LABEL: test_vstl3: 649 ; CHECK: vstl %v24, %r3, 0({{%r[1-5]}}) 650 ; CHECK: br %r14 651 %ptr = getelementptr i8, i8 *%base, i64 4096 652 call void @llvm.s390.vstl(<16 x i8> %vec, i32 %length, i8 *%ptr) 653 ret void 654 } 655 656 ; Check that VSTL doesn't allow an index. 657 define void @test_vstl4(<16 x i8> %vec, i8 *%base, i64 %index, i32 %length) { 658 ; CHECK-LABEL: test_vstl4: 659 ; CHECK: vstl %v24, %r4, 0({{%r[1-5]}}) 660 ; CHECK: br %r14 661 %ptr = getelementptr i8, i8 *%base, i64 %index 662 call void @llvm.s390.vstl(<16 x i8> %vec, i32 %length, i8 *%ptr) 663 ret void 664 } 665 666 ; VUPHB. 667 define <8 x i16> @test_vuphb(<16 x i8> %a) { 668 ; CHECK-LABEL: test_vuphb: 669 ; CHECK: vuphb %v24, %v24 670 ; CHECK: br %r14 671 %res = call <8 x i16> @llvm.s390.vuphb(<16 x i8> %a) 672 ret <8 x i16> %res 673 } 674 675 ; VUPHH. 676 define <4 x i32> @test_vuphh(<8 x i16> %a) { 677 ; CHECK-LABEL: test_vuphh: 678 ; CHECK: vuphh %v24, %v24 679 ; CHECK: br %r14 680 %res = call <4 x i32> @llvm.s390.vuphh(<8 x i16> %a) 681 ret <4 x i32> %res 682 } 683 684 ; VUPHF. 685 define <2 x i64> @test_vuphf(<4 x i32> %a) { 686 ; CHECK-LABEL: test_vuphf: 687 ; CHECK: vuphf %v24, %v24 688 ; CHECK: br %r14 689 %res = call <2 x i64> @llvm.s390.vuphf(<4 x i32> %a) 690 ret <2 x i64> %res 691 } 692 693 ; VUPLHB. 694 define <8 x i16> @test_vuplhb(<16 x i8> %a) { 695 ; CHECK-LABEL: test_vuplhb: 696 ; CHECK: vuplhb %v24, %v24 697 ; CHECK: br %r14 698 %res = call <8 x i16> @llvm.s390.vuplhb(<16 x i8> %a) 699 ret <8 x i16> %res 700 } 701 702 ; VUPLHH. 703 define <4 x i32> @test_vuplhh(<8 x i16> %a) { 704 ; CHECK-LABEL: test_vuplhh: 705 ; CHECK: vuplhh %v24, %v24 706 ; CHECK: br %r14 707 %res = call <4 x i32> @llvm.s390.vuplhh(<8 x i16> %a) 708 ret <4 x i32> %res 709 } 710 711 ; VUPLHF. 712 define <2 x i64> @test_vuplhf(<4 x i32> %a) { 713 ; CHECK-LABEL: test_vuplhf: 714 ; CHECK: vuplhf %v24, %v24 715 ; CHECK: br %r14 716 %res = call <2 x i64> @llvm.s390.vuplhf(<4 x i32> %a) 717 ret <2 x i64> %res 718 } 719 720 ; VUPLB. 721 define <8 x i16> @test_vuplb(<16 x i8> %a) { 722 ; CHECK-LABEL: test_vuplb: 723 ; CHECK: vuplb %v24, %v24 724 ; CHECK: br %r14 725 %res = call <8 x i16> @llvm.s390.vuplb(<16 x i8> %a) 726 ret <8 x i16> %res 727 } 728 729 ; VUPLHW. 730 define <4 x i32> @test_vuplhw(<8 x i16> %a) { 731 ; CHECK-LABEL: test_vuplhw: 732 ; CHECK: vuplhw %v24, %v24 733 ; CHECK: br %r14 734 %res = call <4 x i32> @llvm.s390.vuplhw(<8 x i16> %a) 735 ret <4 x i32> %res 736 } 737 738 ; VUPLF. 739 define <2 x i64> @test_vuplf(<4 x i32> %a) { 740 ; CHECK-LABEL: test_vuplf: 741 ; CHECK: vuplf %v24, %v24 742 ; CHECK: br %r14 743 %res = call <2 x i64> @llvm.s390.vuplf(<4 x i32> %a) 744 ret <2 x i64> %res 745 } 746 747 ; VUPLLB. 748 define <8 x i16> @test_vupllb(<16 x i8> %a) { 749 ; CHECK-LABEL: test_vupllb: 750 ; CHECK: vupllb %v24, %v24 751 ; CHECK: br %r14 752 %res = call <8 x i16> @llvm.s390.vupllb(<16 x i8> %a) 753 ret <8 x i16> %res 754 } 755 756 ; VUPLLH. 757 define <4 x i32> @test_vupllh(<8 x i16> %a) { 758 ; CHECK-LABEL: test_vupllh: 759 ; CHECK: vupllh %v24, %v24 760 ; CHECK: br %r14 761 %res = call <4 x i32> @llvm.s390.vupllh(<8 x i16> %a) 762 ret <4 x i32> %res 763 } 764 765 ; VUPLLF. 766 define <2 x i64> @test_vupllf(<4 x i32> %a) { 767 ; CHECK-LABEL: test_vupllf: 768 ; CHECK: vupllf %v24, %v24 769 ; CHECK: br %r14 770 %res = call <2 x i64> @llvm.s390.vupllf(<4 x i32> %a) 771 ret <2 x i64> %res 772 } 773 774 ; VACCB. 775 define <16 x i8> @test_vaccb(<16 x i8> %a, <16 x i8> %b) { 776 ; CHECK-LABEL: test_vaccb: 777 ; CHECK: vaccb %v24, %v24, %v26 778 ; CHECK: br %r14 779 %res = call <16 x i8> @llvm.s390.vaccb(<16 x i8> %a, <16 x i8> %b) 780 ret <16 x i8> %res 781 } 782 783 ; VACCH. 784 define <8 x i16> @test_vacch(<8 x i16> %a, <8 x i16> %b) { 785 ; CHECK-LABEL: test_vacch: 786 ; CHECK: vacch %v24, %v24, %v26 787 ; CHECK: br %r14 788 %res = call <8 x i16> @llvm.s390.vacch(<8 x i16> %a, <8 x i16> %b) 789 ret <8 x i16> %res 790 } 791 792 ; VACCF. 793 define <4 x i32> @test_vaccf(<4 x i32> %a, <4 x i32> %b) { 794 ; CHECK-LABEL: test_vaccf: 795 ; CHECK: vaccf %v24, %v24, %v26 796 ; CHECK: br %r14 797 %res = call <4 x i32> @llvm.s390.vaccf(<4 x i32> %a, <4 x i32> %b) 798 ret <4 x i32> %res 799 } 800 801 ; VACCG. 802 define <2 x i64> @test_vaccg(<2 x i64> %a, <2 x i64> %b) { 803 ; CHECK-LABEL: test_vaccg: 804 ; CHECK: vaccg %v24, %v24, %v26 805 ; CHECK: br %r14 806 %res = call <2 x i64> @llvm.s390.vaccg(<2 x i64> %a, <2 x i64> %b) 807 ret <2 x i64> %res 808 } 809 810 ; VAQ. 811 define <16 x i8> @test_vaq(<16 x i8> %a, <16 x i8> %b) { 812 ; CHECK-LABEL: test_vaq: 813 ; CHECK: vaq %v24, %v24, %v26 814 ; CHECK: br %r14 815 %res = call <16 x i8> @llvm.s390.vaq(<16 x i8> %a, <16 x i8> %b) 816 ret <16 x i8> %res 817 } 818 819 ; VACQ. 820 define <16 x i8> @test_vacq(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) { 821 ; CHECK-LABEL: test_vacq: 822 ; CHECK: vacq %v24, %v24, %v26, %v28 823 ; CHECK: br %r14 824 %res = call <16 x i8> @llvm.s390.vacq(<16 x i8> %a, <16 x i8> %b, 825 <16 x i8> %c) 826 ret <16 x i8> %res 827 } 828 829 ; VACCQ. 830 define <16 x i8> @test_vaccq(<16 x i8> %a, <16 x i8> %b) { 831 ; CHECK-LABEL: test_vaccq: 832 ; CHECK: vaccq %v24, %v24, %v26 833 ; CHECK: br %r14 834 %res = call <16 x i8> @llvm.s390.vaccq(<16 x i8> %a, <16 x i8> %b) 835 ret <16 x i8> %res 836 } 837 838 ; VACCCQ. 839 define <16 x i8> @test_vacccq(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) { 840 ; CHECK-LABEL: test_vacccq: 841 ; CHECK: vacccq %v24, %v24, %v26, %v28 842 ; CHECK: br %r14 843 %res = call <16 x i8> @llvm.s390.vacccq(<16 x i8> %a, <16 x i8> %b, 844 <16 x i8> %c) 845 ret <16 x i8> %res 846 } 847 848 ; VAVGB. 849 define <16 x i8> @test_vavgb(<16 x i8> %a, <16 x i8> %b) { 850 ; CHECK-LABEL: test_vavgb: 851 ; CHECK: vavgb %v24, %v24, %v26 852 ; CHECK: br %r14 853 %res = call <16 x i8> @llvm.s390.vavgb(<16 x i8> %a, <16 x i8> %b) 854 ret <16 x i8> %res 855 } 856 857 ; VAVGH. 858 define <8 x i16> @test_vavgh(<8 x i16> %a, <8 x i16> %b) { 859 ; CHECK-LABEL: test_vavgh: 860 ; CHECK: vavgh %v24, %v24, %v26 861 ; CHECK: br %r14 862 %res = call <8 x i16> @llvm.s390.vavgh(<8 x i16> %a, <8 x i16> %b) 863 ret <8 x i16> %res 864 } 865 866 ; VAVGF. 867 define <4 x i32> @test_vavgf(<4 x i32> %a, <4 x i32> %b) { 868 ; CHECK-LABEL: test_vavgf: 869 ; CHECK: vavgf %v24, %v24, %v26 870 ; CHECK: br %r14 871 %res = call <4 x i32> @llvm.s390.vavgf(<4 x i32> %a, <4 x i32> %b) 872 ret <4 x i32> %res 873 } 874 875 ; VAVGG. 876 define <2 x i64> @test_vavgg(<2 x i64> %a, <2 x i64> %b) { 877 ; CHECK-LABEL: test_vavgg: 878 ; CHECK: vavgg %v24, %v24, %v26 879 ; CHECK: br %r14 880 %res = call <2 x i64> @llvm.s390.vavgg(<2 x i64> %a, <2 x i64> %b) 881 ret <2 x i64> %res 882 } 883 884 ; VAVGLB. 885 define <16 x i8> @test_vavglb(<16 x i8> %a, <16 x i8> %b) { 886 ; CHECK-LABEL: test_vavglb: 887 ; CHECK: vavglb %v24, %v24, %v26 888 ; CHECK: br %r14 889 %res = call <16 x i8> @llvm.s390.vavglb(<16 x i8> %a, <16 x i8> %b) 890 ret <16 x i8> %res 891 } 892 893 ; VAVGLH. 894 define <8 x i16> @test_vavglh(<8 x i16> %a, <8 x i16> %b) { 895 ; CHECK-LABEL: test_vavglh: 896 ; CHECK: vavglh %v24, %v24, %v26 897 ; CHECK: br %r14 898 %res = call <8 x i16> @llvm.s390.vavglh(<8 x i16> %a, <8 x i16> %b) 899 ret <8 x i16> %res 900 } 901 902 ; VAVGLF. 903 define <4 x i32> @test_vavglf(<4 x i32> %a, <4 x i32> %b) { 904 ; CHECK-LABEL: test_vavglf: 905 ; CHECK: vavglf %v24, %v24, %v26 906 ; CHECK: br %r14 907 %res = call <4 x i32> @llvm.s390.vavglf(<4 x i32> %a, <4 x i32> %b) 908 ret <4 x i32> %res 909 } 910 911 ; VAVGLG. 912 define <2 x i64> @test_vavglg(<2 x i64> %a, <2 x i64> %b) { 913 ; CHECK-LABEL: test_vavglg: 914 ; CHECK: vavglg %v24, %v24, %v26 915 ; CHECK: br %r14 916 %res = call <2 x i64> @llvm.s390.vavglg(<2 x i64> %a, <2 x i64> %b) 917 ret <2 x i64> %res 918 } 919 920 ; VCKSM. 921 define <4 x i32> @test_vcksm(<4 x i32> %a, <4 x i32> %b) { 922 ; CHECK-LABEL: test_vcksm: 923 ; CHECK: vcksm %v24, %v24, %v26 924 ; CHECK: br %r14 925 %res = call <4 x i32> @llvm.s390.vcksm(<4 x i32> %a, <4 x i32> %b) 926 ret <4 x i32> %res 927 } 928 929 ; VGFMB. 930 define <8 x i16> @test_vgfmb(<16 x i8> %a, <16 x i8> %b) { 931 ; CHECK-LABEL: test_vgfmb: 932 ; CHECK: vgfmb %v24, %v24, %v26 933 ; CHECK: br %r14 934 %res = call <8 x i16> @llvm.s390.vgfmb(<16 x i8> %a, <16 x i8> %b) 935 ret <8 x i16> %res 936 } 937 938 ; VGFMH. 939 define <4 x i32> @test_vgfmh(<8 x i16> %a, <8 x i16> %b) { 940 ; CHECK-LABEL: test_vgfmh: 941 ; CHECK: vgfmh %v24, %v24, %v26 942 ; CHECK: br %r14 943 %res = call <4 x i32> @llvm.s390.vgfmh(<8 x i16> %a, <8 x i16> %b) 944 ret <4 x i32> %res 945 } 946 947 ; VGFMF. 948 define <2 x i64> @test_vgfmf(<4 x i32> %a, <4 x i32> %b) { 949 ; CHECK-LABEL: test_vgfmf: 950 ; CHECK: vgfmf %v24, %v24, %v26 951 ; CHECK: br %r14 952 %res = call <2 x i64> @llvm.s390.vgfmf(<4 x i32> %a, <4 x i32> %b) 953 ret <2 x i64> %res 954 } 955 956 ; VGFMG. 957 define <16 x i8> @test_vgfmg(<2 x i64> %a, <2 x i64> %b) { 958 ; CHECK-LABEL: test_vgfmg: 959 ; CHECK: vgfmg %v24, %v24, %v26 960 ; CHECK: br %r14 961 %res = call <16 x i8> @llvm.s390.vgfmg(<2 x i64> %a, <2 x i64> %b) 962 ret <16 x i8> %res 963 } 964 965 ; VGFMAB. 966 define <8 x i16> @test_vgfmab(<16 x i8> %a, <16 x i8> %b, <8 x i16> %c) { 967 ; CHECK-LABEL: test_vgfmab: 968 ; CHECK: vgfmab %v24, %v24, %v26, %v28 969 ; CHECK: br %r14 970 %res = call <8 x i16> @llvm.s390.vgfmab(<16 x i8> %a, <16 x i8> %b, 971 <8 x i16> %c) 972 ret <8 x i16> %res 973 } 974 975 ; VGFMAH. 976 define <4 x i32> @test_vgfmah(<8 x i16> %a, <8 x i16> %b, <4 x i32> %c) { 977 ; CHECK-LABEL: test_vgfmah: 978 ; CHECK: vgfmah %v24, %v24, %v26, %v28 979 ; CHECK: br %r14 980 %res = call <4 x i32> @llvm.s390.vgfmah(<8 x i16> %a, <8 x i16> %b, 981 <4 x i32> %c) 982 ret <4 x i32> %res 983 } 984 985 ; VGFMAF. 986 define <2 x i64> @test_vgfmaf(<4 x i32> %a, <4 x i32> %b, <2 x i64> %c) { 987 ; CHECK-LABEL: test_vgfmaf: 988 ; CHECK: vgfmaf %v24, %v24, %v26, %v28 989 ; CHECK: br %r14 990 %res = call <2 x i64> @llvm.s390.vgfmaf(<4 x i32> %a, <4 x i32> %b, 991 <2 x i64> %c) 992 ret <2 x i64> %res 993 } 994 995 ; VGFMAG. 996 define <16 x i8> @test_vgfmag(<2 x i64> %a, <2 x i64> %b, <16 x i8> %c) { 997 ; CHECK-LABEL: test_vgfmag: 998 ; CHECK: vgfmag %v24, %v24, %v26, %v28 999 ; CHECK: br %r14 1000 %res = call <16 x i8> @llvm.s390.vgfmag(<2 x i64> %a, <2 x i64> %b, 1001 <16 x i8> %c) 1002 ret <16 x i8> %res 1003 } 1004 1005 ; VMAHB. 1006 define <16 x i8> @test_vmahb(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) { 1007 ; CHECK-LABEL: test_vmahb: 1008 ; CHECK: vmahb %v24, %v24, %v26, %v28 1009 ; CHECK: br %r14 1010 %res = call <16 x i8> @llvm.s390.vmahb(<16 x i8> %a, <16 x i8> %b, 1011 <16 x i8> %c) 1012 ret <16 x i8> %res 1013 } 1014 1015 ; VMAHH. 1016 define <8 x i16> @test_vmahh(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) { 1017 ; CHECK-LABEL: test_vmahh: 1018 ; CHECK: vmahh %v24, %v24, %v26, %v28 1019 ; CHECK: br %r14 1020 %res = call <8 x i16> @llvm.s390.vmahh(<8 x i16> %a, <8 x i16> %b, 1021 <8 x i16> %c) 1022 ret <8 x i16> %res 1023 } 1024 1025 ; VMAHF. 1026 define <4 x i32> @test_vmahf(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) { 1027 ; CHECK-LABEL: test_vmahf: 1028 ; CHECK: vmahf %v24, %v24, %v26, %v28 1029 ; CHECK: br %r14 1030 %res = call <4 x i32> @llvm.s390.vmahf(<4 x i32> %a, <4 x i32> %b, 1031 <4 x i32> %c) 1032 ret <4 x i32> %res 1033 } 1034 1035 ; VMALHB. 1036 define <16 x i8> @test_vmalhb(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) { 1037 ; CHECK-LABEL: test_vmalhb: 1038 ; CHECK: vmalhb %v24, %v24, %v26, %v28 1039 ; CHECK: br %r14 1040 %res = call <16 x i8> @llvm.s390.vmalhb(<16 x i8> %a, <16 x i8> %b, 1041 <16 x i8> %c) 1042 ret <16 x i8> %res 1043 } 1044 1045 ; VMALHH. 1046 define <8 x i16> @test_vmalhh(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) { 1047 ; CHECK-LABEL: test_vmalhh: 1048 ; CHECK: vmalhh %v24, %v24, %v26, %v28 1049 ; CHECK: br %r14 1050 %res = call <8 x i16> @llvm.s390.vmalhh(<8 x i16> %a, <8 x i16> %b, 1051 <8 x i16> %c) 1052 ret <8 x i16> %res 1053 } 1054 1055 ; VMALHF. 1056 define <4 x i32> @test_vmalhf(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) { 1057 ; CHECK-LABEL: test_vmalhf: 1058 ; CHECK: vmalhf %v24, %v24, %v26, %v28 1059 ; CHECK: br %r14 1060 %res = call <4 x i32> @llvm.s390.vmalhf(<4 x i32> %a, <4 x i32> %b, 1061 <4 x i32> %c) 1062 ret <4 x i32> %res 1063 } 1064 1065 ; VMAEB. 1066 define <8 x i16> @test_vmaeb(<16 x i8> %a, <16 x i8> %b, <8 x i16> %c) { 1067 ; CHECK-LABEL: test_vmaeb: 1068 ; CHECK: vmaeb %v24, %v24, %v26, %v28 1069 ; CHECK: br %r14 1070 %res = call <8 x i16> @llvm.s390.vmaeb(<16 x i8> %a, <16 x i8> %b, 1071 <8 x i16> %c) 1072 ret <8 x i16> %res 1073 } 1074 1075 ; VMAEH. 1076 define <4 x i32> @test_vmaeh(<8 x i16> %a, <8 x i16> %b, <4 x i32> %c) { 1077 ; CHECK-LABEL: test_vmaeh: 1078 ; CHECK: vmaeh %v24, %v24, %v26, %v28 1079 ; CHECK: br %r14 1080 %res = call <4 x i32> @llvm.s390.vmaeh(<8 x i16> %a, <8 x i16> %b, 1081 <4 x i32> %c) 1082 ret <4 x i32> %res 1083 } 1084 1085 ; VMAEF. 1086 define <2 x i64> @test_vmaef(<4 x i32> %a, <4 x i32> %b, <2 x i64> %c) { 1087 ; CHECK-LABEL: test_vmaef: 1088 ; CHECK: vmaef %v24, %v24, %v26, %v28 1089 ; CHECK: br %r14 1090 %res = call <2 x i64> @llvm.s390.vmaef(<4 x i32> %a, <4 x i32> %b, 1091 <2 x i64> %c) 1092 ret <2 x i64> %res 1093 } 1094 1095 ; VMALEB. 1096 define <8 x i16> @test_vmaleb(<16 x i8> %a, <16 x i8> %b, <8 x i16> %c) { 1097 ; CHECK-LABEL: test_vmaleb: 1098 ; CHECK: vmaleb %v24, %v24, %v26, %v28 1099 ; CHECK: br %r14 1100 %res = call <8 x i16> @llvm.s390.vmaleb(<16 x i8> %a, <16 x i8> %b, 1101 <8 x i16> %c) 1102 ret <8 x i16> %res 1103 } 1104 1105 ; VMALEH. 1106 define <4 x i32> @test_vmaleh(<8 x i16> %a, <8 x i16> %b, <4 x i32> %c) { 1107 ; CHECK-LABEL: test_vmaleh: 1108 ; CHECK: vmaleh %v24, %v24, %v26, %v28 1109 ; CHECK: br %r14 1110 %res = call <4 x i32> @llvm.s390.vmaleh(<8 x i16> %a, <8 x i16> %b, 1111 <4 x i32> %c) 1112 ret <4 x i32> %res 1113 } 1114 1115 ; VMALEF. 1116 define <2 x i64> @test_vmalef(<4 x i32> %a, <4 x i32> %b, <2 x i64> %c) { 1117 ; CHECK-LABEL: test_vmalef: 1118 ; CHECK: vmalef %v24, %v24, %v26, %v28 1119 ; CHECK: br %r14 1120 %res = call <2 x i64> @llvm.s390.vmalef(<4 x i32> %a, <4 x i32> %b, 1121 <2 x i64> %c) 1122 ret <2 x i64> %res 1123 } 1124 1125 ; VMAOB. 1126 define <8 x i16> @test_vmaob(<16 x i8> %a, <16 x i8> %b, <8 x i16> %c) { 1127 ; CHECK-LABEL: test_vmaob: 1128 ; CHECK: vmaob %v24, %v24, %v26, %v28 1129 ; CHECK: br %r14 1130 %res = call <8 x i16> @llvm.s390.vmaob(<16 x i8> %a, <16 x i8> %b, 1131 <8 x i16> %c) 1132 ret <8 x i16> %res 1133 } 1134 1135 ; VMAOH. 1136 define <4 x i32> @test_vmaoh(<8 x i16> %a, <8 x i16> %b, <4 x i32> %c) { 1137 ; CHECK-LABEL: test_vmaoh: 1138 ; CHECK: vmaoh %v24, %v24, %v26, %v28 1139 ; CHECK: br %r14 1140 %res = call <4 x i32> @llvm.s390.vmaoh(<8 x i16> %a, <8 x i16> %b, 1141 <4 x i32> %c) 1142 ret <4 x i32> %res 1143 } 1144 1145 ; VMAOF. 1146 define <2 x i64> @test_vmaof(<4 x i32> %a, <4 x i32> %b, <2 x i64> %c) { 1147 ; CHECK-LABEL: test_vmaof: 1148 ; CHECK: vmaof %v24, %v24, %v26, %v28 1149 ; CHECK: br %r14 1150 %res = call <2 x i64> @llvm.s390.vmaof(<4 x i32> %a, <4 x i32> %b, 1151 <2 x i64> %c) 1152 ret <2 x i64> %res 1153 } 1154 1155 ; VMALOB. 1156 define <8 x i16> @test_vmalob(<16 x i8> %a, <16 x i8> %b, <8 x i16> %c) { 1157 ; CHECK-LABEL: test_vmalob: 1158 ; CHECK: vmalob %v24, %v24, %v26, %v28 1159 ; CHECK: br %r14 1160 %res = call <8 x i16> @llvm.s390.vmalob(<16 x i8> %a, <16 x i8> %b, 1161 <8 x i16> %c) 1162 ret <8 x i16> %res 1163 } 1164 1165 ; VMALOH. 1166 define <4 x i32> @test_vmaloh(<8 x i16> %a, <8 x i16> %b, <4 x i32> %c) { 1167 ; CHECK-LABEL: test_vmaloh: 1168 ; CHECK: vmaloh %v24, %v24, %v26, %v28 1169 ; CHECK: br %r14 1170 %res = call <4 x i32> @llvm.s390.vmaloh(<8 x i16> %a, <8 x i16> %b, 1171 <4 x i32> %c) 1172 ret <4 x i32> %res 1173 } 1174 1175 ; VMALOF. 1176 define <2 x i64> @test_vmalof(<4 x i32> %a, <4 x i32> %b, <2 x i64> %c) { 1177 ; CHECK-LABEL: test_vmalof: 1178 ; CHECK: vmalof %v24, %v24, %v26, %v28 1179 ; CHECK: br %r14 1180 %res = call <2 x i64> @llvm.s390.vmalof(<4 x i32> %a, <4 x i32> %b, 1181 <2 x i64> %c) 1182 ret <2 x i64> %res 1183 } 1184 1185 ; VMHB. 1186 define <16 x i8> @test_vmhb(<16 x i8> %a, <16 x i8> %b) { 1187 ; CHECK-LABEL: test_vmhb: 1188 ; CHECK: vmhb %v24, %v24, %v26 1189 ; CHECK: br %r14 1190 %res = call <16 x i8> @llvm.s390.vmhb(<16 x i8> %a, <16 x i8> %b) 1191 ret <16 x i8> %res 1192 } 1193 1194 ; VMHH. 1195 define <8 x i16> @test_vmhh(<8 x i16> %a, <8 x i16> %b) { 1196 ; CHECK-LABEL: test_vmhh: 1197 ; CHECK: vmhh %v24, %v24, %v26 1198 ; CHECK: br %r14 1199 %res = call <8 x i16> @llvm.s390.vmhh(<8 x i16> %a, <8 x i16> %b) 1200 ret <8 x i16> %res 1201 } 1202 1203 ; VMHF. 1204 define <4 x i32> @test_vmhf(<4 x i32> %a, <4 x i32> %b) { 1205 ; CHECK-LABEL: test_vmhf: 1206 ; CHECK: vmhf %v24, %v24, %v26 1207 ; CHECK: br %r14 1208 %res = call <4 x i32> @llvm.s390.vmhf(<4 x i32> %a, <4 x i32> %b) 1209 ret <4 x i32> %res 1210 } 1211 1212 ; VMLHB. 1213 define <16 x i8> @test_vmlhb(<16 x i8> %a, <16 x i8> %b) { 1214 ; CHECK-LABEL: test_vmlhb: 1215 ; CHECK: vmlhb %v24, %v24, %v26 1216 ; CHECK: br %r14 1217 %res = call <16 x i8> @llvm.s390.vmlhb(<16 x i8> %a, <16 x i8> %b) 1218 ret <16 x i8> %res 1219 } 1220 1221 ; VMLHH. 1222 define <8 x i16> @test_vmlhh(<8 x i16> %a, <8 x i16> %b) { 1223 ; CHECK-LABEL: test_vmlhh: 1224 ; CHECK: vmlhh %v24, %v24, %v26 1225 ; CHECK: br %r14 1226 %res = call <8 x i16> @llvm.s390.vmlhh(<8 x i16> %a, <8 x i16> %b) 1227 ret <8 x i16> %res 1228 } 1229 1230 ; VMLHF. 1231 define <4 x i32> @test_vmlhf(<4 x i32> %a, <4 x i32> %b) { 1232 ; CHECK-LABEL: test_vmlhf: 1233 ; CHECK: vmlhf %v24, %v24, %v26 1234 ; CHECK: br %r14 1235 %res = call <4 x i32> @llvm.s390.vmlhf(<4 x i32> %a, <4 x i32> %b) 1236 ret <4 x i32> %res 1237 } 1238 1239 ; VMEB. 1240 define <8 x i16> @test_vmeb(<16 x i8> %a, <16 x i8> %b) { 1241 ; CHECK-LABEL: test_vmeb: 1242 ; CHECK: vmeb %v24, %v24, %v26 1243 ; CHECK: br %r14 1244 %res = call <8 x i16> @llvm.s390.vmeb(<16 x i8> %a, <16 x i8> %b) 1245 ret <8 x i16> %res 1246 } 1247 1248 ; VMEH. 1249 define <4 x i32> @test_vmeh(<8 x i16> %a, <8 x i16> %b) { 1250 ; CHECK-LABEL: test_vmeh: 1251 ; CHECK: vmeh %v24, %v24, %v26 1252 ; CHECK: br %r14 1253 %res = call <4 x i32> @llvm.s390.vmeh(<8 x i16> %a, <8 x i16> %b) 1254 ret <4 x i32> %res 1255 } 1256 1257 ; VMEF. 1258 define <2 x i64> @test_vmef(<4 x i32> %a, <4 x i32> %b) { 1259 ; CHECK-LABEL: test_vmef: 1260 ; CHECK: vmef %v24, %v24, %v26 1261 ; CHECK: br %r14 1262 %res = call <2 x i64> @llvm.s390.vmef(<4 x i32> %a, <4 x i32> %b) 1263 ret <2 x i64> %res 1264 } 1265 1266 ; VMLEB. 1267 define <8 x i16> @test_vmleb(<16 x i8> %a, <16 x i8> %b) { 1268 ; CHECK-LABEL: test_vmleb: 1269 ; CHECK: vmleb %v24, %v24, %v26 1270 ; CHECK: br %r14 1271 %res = call <8 x i16> @llvm.s390.vmleb(<16 x i8> %a, <16 x i8> %b) 1272 ret <8 x i16> %res 1273 } 1274 1275 ; VMLEH. 1276 define <4 x i32> @test_vmleh(<8 x i16> %a, <8 x i16> %b) { 1277 ; CHECK-LABEL: test_vmleh: 1278 ; CHECK: vmleh %v24, %v24, %v26 1279 ; CHECK: br %r14 1280 %res = call <4 x i32> @llvm.s390.vmleh(<8 x i16> %a, <8 x i16> %b) 1281 ret <4 x i32> %res 1282 } 1283 1284 ; VMLEF. 1285 define <2 x i64> @test_vmlef(<4 x i32> %a, <4 x i32> %b) { 1286 ; CHECK-LABEL: test_vmlef: 1287 ; CHECK: vmlef %v24, %v24, %v26 1288 ; CHECK: br %r14 1289 %res = call <2 x i64> @llvm.s390.vmlef(<4 x i32> %a, <4 x i32> %b) 1290 ret <2 x i64> %res 1291 } 1292 1293 ; VMOB. 1294 define <8 x i16> @test_vmob(<16 x i8> %a, <16 x i8> %b) { 1295 ; CHECK-LABEL: test_vmob: 1296 ; CHECK: vmob %v24, %v24, %v26 1297 ; CHECK: br %r14 1298 %res = call <8 x i16> @llvm.s390.vmob(<16 x i8> %a, <16 x i8> %b) 1299 ret <8 x i16> %res 1300 } 1301 1302 ; VMOH. 1303 define <4 x i32> @test_vmoh(<8 x i16> %a, <8 x i16> %b) { 1304 ; CHECK-LABEL: test_vmoh: 1305 ; CHECK: vmoh %v24, %v24, %v26 1306 ; CHECK: br %r14 1307 %res = call <4 x i32> @llvm.s390.vmoh(<8 x i16> %a, <8 x i16> %b) 1308 ret <4 x i32> %res 1309 } 1310 1311 ; VMOF. 1312 define <2 x i64> @test_vmof(<4 x i32> %a, <4 x i32> %b) { 1313 ; CHECK-LABEL: test_vmof: 1314 ; CHECK: vmof %v24, %v24, %v26 1315 ; CHECK: br %r14 1316 %res = call <2 x i64> @llvm.s390.vmof(<4 x i32> %a, <4 x i32> %b) 1317 ret <2 x i64> %res 1318 } 1319 1320 ; VMLOB. 1321 define <8 x i16> @test_vmlob(<16 x i8> %a, <16 x i8> %b) { 1322 ; CHECK-LABEL: test_vmlob: 1323 ; CHECK: vmlob %v24, %v24, %v26 1324 ; CHECK: br %r14 1325 %res = call <8 x i16> @llvm.s390.vmlob(<16 x i8> %a, <16 x i8> %b) 1326 ret <8 x i16> %res 1327 } 1328 1329 ; VMLOH. 1330 define <4 x i32> @test_vmloh(<8 x i16> %a, <8 x i16> %b) { 1331 ; CHECK-LABEL: test_vmloh: 1332 ; CHECK: vmloh %v24, %v24, %v26 1333 ; CHECK: br %r14 1334 %res = call <4 x i32> @llvm.s390.vmloh(<8 x i16> %a, <8 x i16> %b) 1335 ret <4 x i32> %res 1336 } 1337 1338 ; VMLOF. 1339 define <2 x i64> @test_vmlof(<4 x i32> %a, <4 x i32> %b) { 1340 ; CHECK-LABEL: test_vmlof: 1341 ; CHECK: vmlof %v24, %v24, %v26 1342 ; CHECK: br %r14 1343 %res = call <2 x i64> @llvm.s390.vmlof(<4 x i32> %a, <4 x i32> %b) 1344 ret <2 x i64> %res 1345 } 1346 1347 ; VERLLVB. 1348 define <16 x i8> @test_verllvb(<16 x i8> %a, <16 x i8> %b) { 1349 ; CHECK-LABEL: test_verllvb: 1350 ; CHECK: verllvb %v24, %v24, %v26 1351 ; CHECK: br %r14 1352 %res = call <16 x i8> @llvm.s390.verllvb(<16 x i8> %a, <16 x i8> %b) 1353 ret <16 x i8> %res 1354 } 1355 1356 ; VERLLVH. 1357 define <8 x i16> @test_verllvh(<8 x i16> %a, <8 x i16> %b) { 1358 ; CHECK-LABEL: test_verllvh: 1359 ; CHECK: verllvh %v24, %v24, %v26 1360 ; CHECK: br %r14 1361 %res = call <8 x i16> @llvm.s390.verllvh(<8 x i16> %a, <8 x i16> %b) 1362 ret <8 x i16> %res 1363 } 1364 1365 ; VERLLVF. 1366 define <4 x i32> @test_verllvf(<4 x i32> %a, <4 x i32> %b) { 1367 ; CHECK-LABEL: test_verllvf: 1368 ; CHECK: verllvf %v24, %v24, %v26 1369 ; CHECK: br %r14 1370 %res = call <4 x i32> @llvm.s390.verllvf(<4 x i32> %a, <4 x i32> %b) 1371 ret <4 x i32> %res 1372 } 1373 1374 ; VERLLVG. 1375 define <2 x i64> @test_verllvg(<2 x i64> %a, <2 x i64> %b) { 1376 ; CHECK-LABEL: test_verllvg: 1377 ; CHECK: verllvg %v24, %v24, %v26 1378 ; CHECK: br %r14 1379 %res = call <2 x i64> @llvm.s390.verllvg(<2 x i64> %a, <2 x i64> %b) 1380 ret <2 x i64> %res 1381 } 1382 1383 ; VERLLB. 1384 define <16 x i8> @test_verllb(<16 x i8> %a, i32 %b) { 1385 ; CHECK-LABEL: test_verllb: 1386 ; CHECK: verllb %v24, %v24, 0(%r2) 1387 ; CHECK: br %r14 1388 %res = call <16 x i8> @llvm.s390.verllb(<16 x i8> %a, i32 %b) 1389 ret <16 x i8> %res 1390 } 1391 1392 ; VERLLH. 1393 define <8 x i16> @test_verllh(<8 x i16> %a, i32 %b) { 1394 ; CHECK-LABEL: test_verllh: 1395 ; CHECK: verllh %v24, %v24, 0(%r2) 1396 ; CHECK: br %r14 1397 %res = call <8 x i16> @llvm.s390.verllh(<8 x i16> %a, i32 %b) 1398 ret <8 x i16> %res 1399 } 1400 1401 ; VERLLF. 1402 define <4 x i32> @test_verllf(<4 x i32> %a, i32 %b) { 1403 ; CHECK-LABEL: test_verllf: 1404 ; CHECK: verllf %v24, %v24, 0(%r2) 1405 ; CHECK: br %r14 1406 %res = call <4 x i32> @llvm.s390.verllf(<4 x i32> %a, i32 %b) 1407 ret <4 x i32> %res 1408 } 1409 1410 ; VERLLG. 1411 define <2 x i64> @test_verllg(<2 x i64> %a, i32 %b) { 1412 ; CHECK-LABEL: test_verllg: 1413 ; CHECK: verllg %v24, %v24, 0(%r2) 1414 ; CHECK: br %r14 1415 %res = call <2 x i64> @llvm.s390.verllg(<2 x i64> %a, i32 %b) 1416 ret <2 x i64> %res 1417 } 1418 1419 ; VERLLB with the smallest count. 1420 define <16 x i8> @test_verllb_1(<16 x i8> %a) { 1421 ; CHECK-LABEL: test_verllb_1: 1422 ; CHECK: verllb %v24, %v24, 1 1423 ; CHECK: br %r14 1424 %res = call <16 x i8> @llvm.s390.verllb(<16 x i8> %a, i32 1) 1425 ret <16 x i8> %res 1426 } 1427 1428 ; VERLLB with the largest count. 1429 define <16 x i8> @test_verllb_4095(<16 x i8> %a) { 1430 ; CHECK-LABEL: test_verllb_4095: 1431 ; CHECK: verllb %v24, %v24, 4095 1432 ; CHECK: br %r14 1433 %res = call <16 x i8> @llvm.s390.verllb(<16 x i8> %a, i32 4095) 1434 ret <16 x i8> %res 1435 } 1436 1437 ; VERLLB with the largest count + 1. 1438 define <16 x i8> @test_verllb_4096(<16 x i8> %a) { 1439 ; CHECK-LABEL: test_verllb_4096: 1440 ; CHECK: lhi [[REG:%r[1-5]]], 4096 1441 ; CHECK: verllb %v24, %v24, 0([[REG]]) 1442 ; CHECK: br %r14 1443 %res = call <16 x i8> @llvm.s390.verllb(<16 x i8> %a, i32 4096) 1444 ret <16 x i8> %res 1445 } 1446 1447 ; VERIMB. 1448 define <16 x i8> @test_verimb(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) { 1449 ; CHECK-LABEL: test_verimb: 1450 ; CHECK: verimb %v24, %v26, %v28, 1 1451 ; CHECK: br %r14 1452 %res = call <16 x i8> @llvm.s390.verimb(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c, i32 1) 1453 ret <16 x i8> %res 1454 } 1455 1456 ; VERIMH. 1457 define <8 x i16> @test_verimh(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) { 1458 ; CHECK-LABEL: test_verimh: 1459 ; CHECK: verimh %v24, %v26, %v28, 1 1460 ; CHECK: br %r14 1461 %res = call <8 x i16> @llvm.s390.verimh(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c, i32 1) 1462 ret <8 x i16> %res 1463 } 1464 1465 ; VERIMF. 1466 define <4 x i32> @test_verimf(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) { 1467 ; CHECK-LABEL: test_verimf: 1468 ; CHECK: verimf %v24, %v26, %v28, 1 1469 ; CHECK: br %r14 1470 %res = call <4 x i32> @llvm.s390.verimf(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, i32 1) 1471 ret <4 x i32> %res 1472 } 1473 1474 ; VERIMG. 1475 define <2 x i64> @test_verimg(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) { 1476 ; CHECK-LABEL: test_verimg: 1477 ; CHECK: verimg %v24, %v26, %v28, 1 1478 ; CHECK: br %r14 1479 %res = call <2 x i64> @llvm.s390.verimg(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c, i32 1) 1480 ret <2 x i64> %res 1481 } 1482 1483 ; VERIMB with a different mask. 1484 define <16 x i8> @test_verimb_254(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) { 1485 ; CHECK-LABEL: test_verimb_254: 1486 ; CHECK: verimb %v24, %v26, %v28, 254 1487 ; CHECK: br %r14 1488 %res = call <16 x i8> @llvm.s390.verimb(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c, i32 254) 1489 ret <16 x i8> %res 1490 } 1491 1492 ; VSL. 1493 define <16 x i8> @test_vsl(<16 x i8> %a, <16 x i8> %b) { 1494 ; CHECK-LABEL: test_vsl: 1495 ; CHECK: vsl %v24, %v24, %v26 1496 ; CHECK: br %r14 1497 %res = call <16 x i8> @llvm.s390.vsl(<16 x i8> %a, <16 x i8> %b) 1498 ret <16 x i8> %res 1499 } 1500 1501 ; VSLB. 1502 define <16 x i8> @test_vslb(<16 x i8> %a, <16 x i8> %b) { 1503 ; CHECK-LABEL: test_vslb: 1504 ; CHECK: vslb %v24, %v24, %v26 1505 ; CHECK: br %r14 1506 %res = call <16 x i8> @llvm.s390.vslb(<16 x i8> %a, <16 x i8> %b) 1507 ret <16 x i8> %res 1508 } 1509 1510 ; VSRA. 1511 define <16 x i8> @test_vsra(<16 x i8> %a, <16 x i8> %b) { 1512 ; CHECK-LABEL: test_vsra: 1513 ; CHECK: vsra %v24, %v24, %v26 1514 ; CHECK: br %r14 1515 %res = call <16 x i8> @llvm.s390.vsra(<16 x i8> %a, <16 x i8> %b) 1516 ret <16 x i8> %res 1517 } 1518 1519 ; VSRAB. 1520 define <16 x i8> @test_vsrab(<16 x i8> %a, <16 x i8> %b) { 1521 ; CHECK-LABEL: test_vsrab: 1522 ; CHECK: vsrab %v24, %v24, %v26 1523 ; CHECK: br %r14 1524 %res = call <16 x i8> @llvm.s390.vsrab(<16 x i8> %a, <16 x i8> %b) 1525 ret <16 x i8> %res 1526 } 1527 1528 ; VSRL. 1529 define <16 x i8> @test_vsrl(<16 x i8> %a, <16 x i8> %b) { 1530 ; CHECK-LABEL: test_vsrl: 1531 ; CHECK: vsrl %v24, %v24, %v26 1532 ; CHECK: br %r14 1533 %res = call <16 x i8> @llvm.s390.vsrl(<16 x i8> %a, <16 x i8> %b) 1534 ret <16 x i8> %res 1535 } 1536 1537 ; VSRLB. 1538 define <16 x i8> @test_vsrlb(<16 x i8> %a, <16 x i8> %b) { 1539 ; CHECK-LABEL: test_vsrlb: 1540 ; CHECK: vsrlb %v24, %v24, %v26 1541 ; CHECK: br %r14 1542 %res = call <16 x i8> @llvm.s390.vsrlb(<16 x i8> %a, <16 x i8> %b) 1543 ret <16 x i8> %res 1544 } 1545 1546 ; VSLDB with the minimum useful value. 1547 define <16 x i8> @test_vsldb_1(<16 x i8> %a, <16 x i8> %b) { 1548 ; CHECK-LABEL: test_vsldb_1: 1549 ; CHECK: vsldb %v24, %v24, %v26, 1 1550 ; CHECK: br %r14 1551 %res = call <16 x i8> @llvm.s390.vsldb(<16 x i8> %a, <16 x i8> %b, i32 1) 1552 ret <16 x i8> %res 1553 } 1554 1555 ; VSLDB with the maximum value. 1556 define <16 x i8> @test_vsldb_15(<16 x i8> %a, <16 x i8> %b) { 1557 ; CHECK-LABEL: test_vsldb_15: 1558 ; CHECK: vsldb %v24, %v24, %v26, 15 1559 ; CHECK: br %r14 1560 %res = call <16 x i8> @llvm.s390.vsldb(<16 x i8> %a, <16 x i8> %b, i32 15) 1561 ret <16 x i8> %res 1562 } 1563 1564 ; VSCBIB. 1565 define <16 x i8> @test_vscbib(<16 x i8> %a, <16 x i8> %b) { 1566 ; CHECK-LABEL: test_vscbib: 1567 ; CHECK: vscbib %v24, %v24, %v26 1568 ; CHECK: br %r14 1569 %res = call <16 x i8> @llvm.s390.vscbib(<16 x i8> %a, <16 x i8> %b) 1570 ret <16 x i8> %res 1571 } 1572 1573 ; VSCBIH. 1574 define <8 x i16> @test_vscbih(<8 x i16> %a, <8 x i16> %b) { 1575 ; CHECK-LABEL: test_vscbih: 1576 ; CHECK: vscbih %v24, %v24, %v26 1577 ; CHECK: br %r14 1578 %res = call <8 x i16> @llvm.s390.vscbih(<8 x i16> %a, <8 x i16> %b) 1579 ret <8 x i16> %res 1580 } 1581 1582 ; VSCBIF. 1583 define <4 x i32> @test_vscbif(<4 x i32> %a, <4 x i32> %b) { 1584 ; CHECK-LABEL: test_vscbif: 1585 ; CHECK: vscbif %v24, %v24, %v26 1586 ; CHECK: br %r14 1587 %res = call <4 x i32> @llvm.s390.vscbif(<4 x i32> %a, <4 x i32> %b) 1588 ret <4 x i32> %res 1589 } 1590 1591 ; VSCBIG. 1592 define <2 x i64> @test_vscbig(<2 x i64> %a, <2 x i64> %b) { 1593 ; CHECK-LABEL: test_vscbig: 1594 ; CHECK: vscbig %v24, %v24, %v26 1595 ; CHECK: br %r14 1596 %res = call <2 x i64> @llvm.s390.vscbig(<2 x i64> %a, <2 x i64> %b) 1597 ret <2 x i64> %res 1598 } 1599 1600 ; VSQ. 1601 define <16 x i8> @test_vsq(<16 x i8> %a, <16 x i8> %b) { 1602 ; CHECK-LABEL: test_vsq: 1603 ; CHECK: vsq %v24, %v24, %v26 1604 ; CHECK: br %r14 1605 %res = call <16 x i8> @llvm.s390.vsq(<16 x i8> %a, <16 x i8> %b) 1606 ret <16 x i8> %res 1607 } 1608 1609 ; VSBIQ. 1610 define <16 x i8> @test_vsbiq(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) { 1611 ; CHECK-LABEL: test_vsbiq: 1612 ; CHECK: vsbiq %v24, %v24, %v26, %v28 1613 ; CHECK: br %r14 1614 %res = call <16 x i8> @llvm.s390.vsbiq(<16 x i8> %a, <16 x i8> %b, 1615 <16 x i8> %c) 1616 ret <16 x i8> %res 1617 } 1618 1619 ; VSCBIQ. 1620 define <16 x i8> @test_vscbiq(<16 x i8> %a, <16 x i8> %b) { 1621 ; CHECK-LABEL: test_vscbiq: 1622 ; CHECK: vscbiq %v24, %v24, %v26 1623 ; CHECK: br %r14 1624 %res = call <16 x i8> @llvm.s390.vscbiq(<16 x i8> %a, <16 x i8> %b) 1625 ret <16 x i8> %res 1626 } 1627 1628 ; VSBCBIQ. 1629 define <16 x i8> @test_vsbcbiq(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) { 1630 ; CHECK-LABEL: test_vsbcbiq: 1631 ; CHECK: vsbcbiq %v24, %v24, %v26, %v28 1632 ; CHECK: br %r14 1633 %res = call <16 x i8> @llvm.s390.vsbcbiq(<16 x i8> %a, <16 x i8> %b, 1634 <16 x i8> %c) 1635 ret <16 x i8> %res 1636 } 1637 1638 ; VSUMB. 1639 define <4 x i32> @test_vsumb(<16 x i8> %a, <16 x i8> %b) { 1640 ; CHECK-LABEL: test_vsumb: 1641 ; CHECK: vsumb %v24, %v24, %v26 1642 ; CHECK: br %r14 1643 %res = call <4 x i32> @llvm.s390.vsumb(<16 x i8> %a, <16 x i8> %b) 1644 ret <4 x i32> %res 1645 } 1646 1647 ; VSUMH. 1648 define <4 x i32> @test_vsumh(<8 x i16> %a, <8 x i16> %b) { 1649 ; CHECK-LABEL: test_vsumh: 1650 ; CHECK: vsumh %v24, %v24, %v26 1651 ; CHECK: br %r14 1652 %res = call <4 x i32> @llvm.s390.vsumh(<8 x i16> %a, <8 x i16> %b) 1653 ret <4 x i32> %res 1654 } 1655 1656 ; VSUMGH. 1657 define <2 x i64> @test_vsumgh(<8 x i16> %a, <8 x i16> %b) { 1658 ; CHECK-LABEL: test_vsumgh: 1659 ; CHECK: vsumgh %v24, %v24, %v26 1660 ; CHECK: br %r14 1661 %res = call <2 x i64> @llvm.s390.vsumgh(<8 x i16> %a, <8 x i16> %b) 1662 ret <2 x i64> %res 1663 } 1664 1665 ; VSUMGF. 1666 define <2 x i64> @test_vsumgf(<4 x i32> %a, <4 x i32> %b) { 1667 ; CHECK-LABEL: test_vsumgf: 1668 ; CHECK: vsumgf %v24, %v24, %v26 1669 ; CHECK: br %r14 1670 %res = call <2 x i64> @llvm.s390.vsumgf(<4 x i32> %a, <4 x i32> %b) 1671 ret <2 x i64> %res 1672 } 1673 1674 ; VSUMQF. 1675 define <16 x i8> @test_vsumqf(<4 x i32> %a, <4 x i32> %b) { 1676 ; CHECK-LABEL: test_vsumqf: 1677 ; CHECK: vsumqf %v24, %v24, %v26 1678 ; CHECK: br %r14 1679 %res = call <16 x i8> @llvm.s390.vsumqf(<4 x i32> %a, <4 x i32> %b) 1680 ret <16 x i8> %res 1681 } 1682 1683 ; VSUMQG. 1684 define <16 x i8> @test_vsumqg(<2 x i64> %a, <2 x i64> %b) { 1685 ; CHECK-LABEL: test_vsumqg: 1686 ; CHECK: vsumqg %v24, %v24, %v26 1687 ; CHECK: br %r14 1688 %res = call <16 x i8> @llvm.s390.vsumqg(<2 x i64> %a, <2 x i64> %b) 1689 ret <16 x i8> %res 1690 } 1691 1692 ; VTM with no processing of the result. 1693 define i32 @test_vtm(<16 x i8> %a, <16 x i8> %b) { 1694 ; CHECK-LABEL: test_vtm: 1695 ; CHECK: vtm %v24, %v26 1696 ; CHECK: ipm %r2 1697 ; CHECK: srl %r2, 28 1698 ; CHECK: br %r14 1699 %res = call i32 @llvm.s390.vtm(<16 x i8> %a, <16 x i8> %b) 1700 ret i32 %res 1701 } 1702 1703 ; VTM, storing to %ptr if all bits are set. 1704 define void @test_vtm_all_store(<16 x i8> %a, <16 x i8> %b, i32 *%ptr) { 1705 ; CHECK-LABEL: test_vtm_all_store: 1706 ; CHECK-NOT: %r 1707 ; CHECK: vtm %v24, %v26 1708 ; CHECK-NEXT: {{bnor|bler}} %r14 1709 ; CHECK: mvhi 0(%r2), 0 1710 ; CHECK: br %r14 1711 %res = call i32 @llvm.s390.vtm(<16 x i8> %a, <16 x i8> %b) 1712 %cmp = icmp sge i32 %res, 3 1713 br i1 %cmp, label %store, label %exit 1714 1715 store: 1716 store i32 0, i32 *%ptr 1717 br label %exit 1718 1719 exit: 1720 ret void 1721 } 1722 1723 ; VCEQBS with no processing of the result. 1724 define i32 @test_vceqbs(<16 x i8> %a, <16 x i8> %b) { 1725 ; CHECK-LABEL: test_vceqbs: 1726 ; CHECK: vceqbs {{%v[0-9]+}}, %v24, %v26 1727 ; CHECK: ipm %r2 1728 ; CHECK: srl %r2, 28 1729 ; CHECK: br %r14 1730 %call = call {<16 x i8>, i32} @llvm.s390.vceqbs(<16 x i8> %a, <16 x i8> %b) 1731 %res = extractvalue {<16 x i8>, i32} %call, 1 1732 ret i32 %res 1733 } 1734 1735 ; VCEQBS, returning 1 if any elements are equal (CC != 3). 1736 define i32 @test_vceqbs_any_bool(<16 x i8> %a, <16 x i8> %b) { 1737 ; CHECK-LABEL: test_vceqbs_any_bool: 1738 ; CHECK: vceqbs {{%v[0-9]+}}, %v24, %v26 1739 ; CHECK: lhi %r2, 0 1740 ; CHECK: lochile %r2, 1 1741 ; CHECK: br %r14 1742 %call = call {<16 x i8>, i32} @llvm.s390.vceqbs(<16 x i8> %a, <16 x i8> %b) 1743 %res = extractvalue {<16 x i8>, i32} %call, 1 1744 %cmp = icmp ne i32 %res, 3 1745 %ext = zext i1 %cmp to i32 1746 ret i32 %ext 1747 } 1748 1749 ; VCEQBS, storing to %ptr if any elements are equal. 1750 define <16 x i8> @test_vceqbs_any_store(<16 x i8> %a, <16 x i8> %b, i32 *%ptr) { 1751 ; CHECK-LABEL: test_vceqbs_any_store: 1752 ; CHECK-NOT: %r 1753 ; CHECK: vceqbs %v24, %v24, %v26 1754 ; CHECK-NEXT: {{bor|bnler}} %r14 1755 ; CHECK: mvhi 0(%r2), 0 1756 ; CHECK: br %r14 1757 %call = call {<16 x i8>, i32} @llvm.s390.vceqbs(<16 x i8> %a, <16 x i8> %b) 1758 %res = extractvalue {<16 x i8>, i32} %call, 0 1759 %cc = extractvalue {<16 x i8>, i32} %call, 1 1760 %cmp = icmp ule i32 %cc, 2 1761 br i1 %cmp, label %store, label %exit 1762 1763 store: 1764 store i32 0, i32 *%ptr 1765 br label %exit 1766 1767 exit: 1768 ret <16 x i8> %res 1769 } 1770 1771 ; VCEQHS with no processing of the result. 1772 define i32 @test_vceqhs(<8 x i16> %a, <8 x i16> %b) { 1773 ; CHECK-LABEL: test_vceqhs: 1774 ; CHECK: vceqhs {{%v[0-9]+}}, %v24, %v26 1775 ; CHECK: ipm %r2 1776 ; CHECK: srl %r2, 28 1777 ; CHECK: br %r14 1778 %call = call {<8 x i16>, i32} @llvm.s390.vceqhs(<8 x i16> %a, <8 x i16> %b) 1779 %res = extractvalue {<8 x i16>, i32} %call, 1 1780 ret i32 %res 1781 } 1782 1783 ; VCEQHS, returning 1 if not all elements are equal. 1784 define i32 @test_vceqhs_notall_bool(<8 x i16> %a, <8 x i16> %b) { 1785 ; CHECK-LABEL: test_vceqhs_notall_bool: 1786 ; CHECK: vceqhs {{%v[0-9]+}}, %v24, %v26 1787 ; CHECK: lhi %r2, 0 1788 ; CHECK: lochinhe %r2, 1 1789 ; CHECK: br %r14 1790 %call = call {<8 x i16>, i32} @llvm.s390.vceqhs(<8 x i16> %a, <8 x i16> %b) 1791 %res = extractvalue {<8 x i16>, i32} %call, 1 1792 %cmp = icmp sge i32 %res, 1 1793 %ext = zext i1 %cmp to i32 1794 ret i32 %ext 1795 } 1796 1797 ; VCEQHS, storing to %ptr if not all elements are equal. 1798 define <8 x i16> @test_vceqhs_notall_store(<8 x i16> %a, <8 x i16> %b, 1799 i32 *%ptr) { 1800 ; CHECK-LABEL: test_vceqhs_notall_store: 1801 ; CHECK-NOT: %r 1802 ; CHECK: vceqhs %v24, %v24, %v26 1803 ; CHECK-NEXT: {{bher|ber}} %r14 1804 ; CHECK: mvhi 0(%r2), 0 1805 ; CHECK: br %r14 1806 %call = call {<8 x i16>, i32} @llvm.s390.vceqhs(<8 x i16> %a, <8 x i16> %b) 1807 %res = extractvalue {<8 x i16>, i32} %call, 0 1808 %cc = extractvalue {<8 x i16>, i32} %call, 1 1809 %cmp = icmp ugt i32 %cc, 0 1810 br i1 %cmp, label %store, label %exit 1811 1812 store: 1813 store i32 0, i32 *%ptr 1814 br label %exit 1815 1816 exit: 1817 ret <8 x i16> %res 1818 } 1819 1820 ; VCEQFS with no processing of the result. 1821 define i32 @test_vceqfs(<4 x i32> %a, <4 x i32> %b) { 1822 ; CHECK-LABEL: test_vceqfs: 1823 ; CHECK: vceqfs {{%v[0-9]+}}, %v24, %v26 1824 ; CHECK: ipm %r2 1825 ; CHECK: srl %r2, 28 1826 ; CHECK: br %r14 1827 %call = call {<4 x i32>, i32} @llvm.s390.vceqfs(<4 x i32> %a, <4 x i32> %b) 1828 %res = extractvalue {<4 x i32>, i32} %call, 1 1829 ret i32 %res 1830 } 1831 1832 ; VCEQFS, returning 1 if no elements are equal. 1833 define i32 @test_vceqfs_none_bool(<4 x i32> %a, <4 x i32> %b) { 1834 ; CHECK-LABEL: test_vceqfs_none_bool: 1835 ; CHECK: vceqfs {{%v[0-9]+}}, %v24, %v26 1836 ; CHECK: lhi %r2, 0 1837 ; CHECK: lochio %r2, 1 1838 ; CHECK: br %r14 1839 %call = call {<4 x i32>, i32} @llvm.s390.vceqfs(<4 x i32> %a, <4 x i32> %b) 1840 %res = extractvalue {<4 x i32>, i32} %call, 1 1841 %cmp = icmp eq i32 %res, 3 1842 %ext = zext i1 %cmp to i32 1843 ret i32 %ext 1844 } 1845 1846 ; VCEQFS, storing to %ptr if no elements are equal. 1847 define <4 x i32> @test_vceqfs_none_store(<4 x i32> %a, <4 x i32> %b, 1848 i32 *%ptr) { 1849 ; CHECK-LABEL: test_vceqfs_none_store: 1850 ; CHECK-NOT: %r 1851 ; CHECK: vceqfs %v24, %v24, %v26 1852 ; CHECK-NEXT: {{bnor|bler}} %r14 1853 ; CHECK: mvhi 0(%r2), 0 1854 ; CHECK: br %r14 1855 %call = call {<4 x i32>, i32} @llvm.s390.vceqfs(<4 x i32> %a, <4 x i32> %b) 1856 %res = extractvalue {<4 x i32>, i32} %call, 0 1857 %cc = extractvalue {<4 x i32>, i32} %call, 1 1858 %cmp = icmp uge i32 %cc, 3 1859 br i1 %cmp, label %store, label %exit 1860 1861 store: 1862 store i32 0, i32 *%ptr 1863 br label %exit 1864 1865 exit: 1866 ret <4 x i32> %res 1867 } 1868 1869 ; VCEQGS with no processing of the result. 1870 define i32 @test_vceqgs(<2 x i64> %a, <2 x i64> %b) { 1871 ; CHECK-LABEL: test_vceqgs: 1872 ; CHECK: vceqgs {{%v[0-9]+}}, %v24, %v26 1873 ; CHECK: ipm %r2 1874 ; CHECK: srl %r2, 28 1875 ; CHECK: br %r14 1876 %call = call {<2 x i64>, i32} @llvm.s390.vceqgs(<2 x i64> %a, <2 x i64> %b) 1877 %res = extractvalue {<2 x i64>, i32} %call, 1 1878 ret i32 %res 1879 } 1880 1881 ; VCEQGS returning 1 if all elements are equal (CC == 0). 1882 define i32 @test_vceqgs_all_bool(<2 x i64> %a, <2 x i64> %b) { 1883 ; CHECK-LABEL: test_vceqgs_all_bool: 1884 ; CHECK: vceqgs {{%v[0-9]+}}, %v24, %v26 1885 ; CHECK: lhi %r2, 0 1886 ; CHECK: lochie %r2, 1 1887 ; CHECK: br %r14 1888 %call = call {<2 x i64>, i32} @llvm.s390.vceqgs(<2 x i64> %a, <2 x i64> %b) 1889 %res = extractvalue {<2 x i64>, i32} %call, 1 1890 %cmp = icmp ult i32 %res, 1 1891 %ext = zext i1 %cmp to i32 1892 ret i32 %ext 1893 } 1894 1895 ; VCEQGS, storing to %ptr if all elements are equal. 1896 define <2 x i64> @test_vceqgs_all_store(<2 x i64> %a, <2 x i64> %b, i32 *%ptr) { 1897 ; CHECK-LABEL: test_vceqgs_all_store: 1898 ; CHECK-NOT: %r 1899 ; CHECK: vceqgs %v24, %v24, %v26 1900 ; CHECK-NEXT: {{bnher|bner}} %r14 1901 ; CHECK: mvhi 0(%r2), 0 1902 ; CHECK: br %r14 1903 %call = call {<2 x i64>, i32} @llvm.s390.vceqgs(<2 x i64> %a, <2 x i64> %b) 1904 %res = extractvalue {<2 x i64>, i32} %call, 0 1905 %cc = extractvalue {<2 x i64>, i32} %call, 1 1906 %cmp = icmp sle i32 %cc, 0 1907 br i1 %cmp, label %store, label %exit 1908 1909 store: 1910 store i32 0, i32 *%ptr 1911 br label %exit 1912 1913 exit: 1914 ret <2 x i64> %res 1915 } 1916 1917 ; VCHBS with no processing of the result. 1918 define i32 @test_vchbs(<16 x i8> %a, <16 x i8> %b) { 1919 ; CHECK-LABEL: test_vchbs: 1920 ; CHECK: vchbs {{%v[0-9]+}}, %v24, %v26 1921 ; CHECK: ipm %r2 1922 ; CHECK: srl %r2, 28 1923 ; CHECK: br %r14 1924 %call = call {<16 x i8>, i32} @llvm.s390.vchbs(<16 x i8> %a, <16 x i8> %b) 1925 %res = extractvalue {<16 x i8>, i32} %call, 1 1926 ret i32 %res 1927 } 1928 1929 ; VCHBS, returning 1 if any elements are higher (CC != 3). 1930 define i32 @test_vchbs_any_bool(<16 x i8> %a, <16 x i8> %b) { 1931 ; CHECK-LABEL: test_vchbs_any_bool: 1932 ; CHECK: vchbs {{%v[0-9]+}}, %v24, %v26 1933 ; CHECK: lhi %r2, 0 1934 ; CHECK: lochile %r2, 1 1935 ; CHECK: br %r14 1936 %call = call {<16 x i8>, i32} @llvm.s390.vchbs(<16 x i8> %a, <16 x i8> %b) 1937 %res = extractvalue {<16 x i8>, i32} %call, 1 1938 %cmp = icmp ne i32 %res, 3 1939 %ext = zext i1 %cmp to i32 1940 ret i32 %ext 1941 } 1942 1943 ; VCHBS, storing to %ptr if any elements are higher. 1944 define <16 x i8> @test_vchbs_any_store(<16 x i8> %a, <16 x i8> %b, i32 *%ptr) { 1945 ; CHECK-LABEL: test_vchbs_any_store: 1946 ; CHECK-NOT: %r 1947 ; CHECK: vchbs %v24, %v24, %v26 1948 ; CHECK-NEXT: {{bor|bnler}} %r14 1949 ; CHECK: mvhi 0(%r2), 0 1950 ; CHECK: br %r14 1951 %call = call {<16 x i8>, i32} @llvm.s390.vchbs(<16 x i8> %a, <16 x i8> %b) 1952 %res = extractvalue {<16 x i8>, i32} %call, 0 1953 %cc = extractvalue {<16 x i8>, i32} %call, 1 1954 %cmp = icmp ule i32 %cc, 2 1955 br i1 %cmp, label %store, label %exit 1956 1957 store: 1958 store i32 0, i32 *%ptr 1959 br label %exit 1960 1961 exit: 1962 ret <16 x i8> %res 1963 } 1964 1965 ; VCHHS with no processing of the result. 1966 define i32 @test_vchhs(<8 x i16> %a, <8 x i16> %b) { 1967 ; CHECK-LABEL: test_vchhs: 1968 ; CHECK: vchhs {{%v[0-9]+}}, %v24, %v26 1969 ; CHECK: ipm %r2 1970 ; CHECK: srl %r2, 28 1971 ; CHECK: br %r14 1972 %call = call {<8 x i16>, i32} @llvm.s390.vchhs(<8 x i16> %a, <8 x i16> %b) 1973 %res = extractvalue {<8 x i16>, i32} %call, 1 1974 ret i32 %res 1975 } 1976 1977 ; VCHHS, returning 1 if not all elements are higher. 1978 define i32 @test_vchhs_notall_bool(<8 x i16> %a, <8 x i16> %b) { 1979 ; CHECK-LABEL: test_vchhs_notall_bool: 1980 ; CHECK: vchhs {{%v[0-9]+}}, %v24, %v26 1981 ; CHECK: lhi %r2, 0 1982 ; CHECK: lochinhe %r2, 1 1983 ; CHECK: br %r14 1984 %call = call {<8 x i16>, i32} @llvm.s390.vchhs(<8 x i16> %a, <8 x i16> %b) 1985 %res = extractvalue {<8 x i16>, i32} %call, 1 1986 %cmp = icmp sge i32 %res, 1 1987 %ext = zext i1 %cmp to i32 1988 ret i32 %ext 1989 } 1990 1991 ; VCHHS, storing to %ptr if not all elements are higher. 1992 define <8 x i16> @test_vchhs_notall_store(<8 x i16> %a, <8 x i16> %b, 1993 i32 *%ptr) { 1994 ; CHECK-LABEL: test_vchhs_notall_store: 1995 ; CHECK-NOT: %r 1996 ; CHECK: vchhs %v24, %v24, %v26 1997 ; CHECK-NEXT: {{bher|ber}} %r14 1998 ; CHECK: mvhi 0(%r2), 0 1999 ; CHECK: br %r14 2000 %call = call {<8 x i16>, i32} @llvm.s390.vchhs(<8 x i16> %a, <8 x i16> %b) 2001 %res = extractvalue {<8 x i16>, i32} %call, 0 2002 %cc = extractvalue {<8 x i16>, i32} %call, 1 2003 %cmp = icmp ugt i32 %cc, 0 2004 br i1 %cmp, label %store, label %exit 2005 2006 store: 2007 store i32 0, i32 *%ptr 2008 br label %exit 2009 2010 exit: 2011 ret <8 x i16> %res 2012 } 2013 2014 ; VCHFS with no processing of the result. 2015 define i32 @test_vchfs(<4 x i32> %a, <4 x i32> %b) { 2016 ; CHECK-LABEL: test_vchfs: 2017 ; CHECK: vchfs {{%v[0-9]+}}, %v24, %v26 2018 ; CHECK: ipm %r2 2019 ; CHECK: srl %r2, 28 2020 ; CHECK: br %r14 2021 %call = call {<4 x i32>, i32} @llvm.s390.vchfs(<4 x i32> %a, <4 x i32> %b) 2022 %res = extractvalue {<4 x i32>, i32} %call, 1 2023 ret i32 %res 2024 } 2025 2026 ; VCHFS, returning 1 if no elements are higher. 2027 define i32 @test_vchfs_none_bool(<4 x i32> %a, <4 x i32> %b) { 2028 ; CHECK-LABEL: test_vchfs_none_bool: 2029 ; CHECK: vchfs {{%v[0-9]+}}, %v24, %v26 2030 ; CHECK: lhi %r2, 0 2031 ; CHECK: lochio %r2, 1 2032 ; CHECK: br %r14 2033 %call = call {<4 x i32>, i32} @llvm.s390.vchfs(<4 x i32> %a, <4 x i32> %b) 2034 %res = extractvalue {<4 x i32>, i32} %call, 1 2035 %cmp = icmp eq i32 %res, 3 2036 %ext = zext i1 %cmp to i32 2037 ret i32 %ext 2038 } 2039 2040 ; VCHFS, storing to %ptr if no elements are higher. 2041 define <4 x i32> @test_vchfs_none_store(<4 x i32> %a, <4 x i32> %b, i32 *%ptr) { 2042 ; CHECK-LABEL: test_vchfs_none_store: 2043 ; CHECK-NOT: %r 2044 ; CHECK: vchfs %v24, %v24, %v26 2045 ; CHECK-NEXT: {{bnor|bler}} %r14 2046 ; CHECK: mvhi 0(%r2), 0 2047 ; CHECK: br %r14 2048 %call = call {<4 x i32>, i32} @llvm.s390.vchfs(<4 x i32> %a, <4 x i32> %b) 2049 %res = extractvalue {<4 x i32>, i32} %call, 0 2050 %cc = extractvalue {<4 x i32>, i32} %call, 1 2051 %cmp = icmp uge i32 %cc, 3 2052 br i1 %cmp, label %store, label %exit 2053 2054 store: 2055 store i32 0, i32 *%ptr 2056 br label %exit 2057 2058 exit: 2059 ret <4 x i32> %res 2060 } 2061 2062 ; VCHGS with no processing of the result. 2063 define i32 @test_vchgs(<2 x i64> %a, <2 x i64> %b) { 2064 ; CHECK-LABEL: test_vchgs: 2065 ; CHECK: vchgs {{%v[0-9]+}}, %v24, %v26 2066 ; CHECK: ipm %r2 2067 ; CHECK: srl %r2, 28 2068 ; CHECK: br %r14 2069 %call = call {<2 x i64>, i32} @llvm.s390.vchgs(<2 x i64> %a, <2 x i64> %b) 2070 %res = extractvalue {<2 x i64>, i32} %call, 1 2071 ret i32 %res 2072 } 2073 2074 ; VCHGS returning 1 if all elements are higher (CC == 0). 2075 define i32 @test_vchgs_all_bool(<2 x i64> %a, <2 x i64> %b) { 2076 ; CHECK-LABEL: test_vchgs_all_bool: 2077 ; CHECK: vchgs {{%v[0-9]+}}, %v24, %v26 2078 ; CHECK: lhi %r2, 0 2079 ; CHECK: lochie %r2, 1 2080 ; CHECK: br %r14 2081 %call = call {<2 x i64>, i32} @llvm.s390.vchgs(<2 x i64> %a, <2 x i64> %b) 2082 %res = extractvalue {<2 x i64>, i32} %call, 1 2083 %cmp = icmp ult i32 %res, 1 2084 %ext = zext i1 %cmp to i32 2085 ret i32 %ext 2086 } 2087 2088 ; VCHGS, storing to %ptr if all elements are higher. 2089 define <2 x i64> @test_vchgs_all_store(<2 x i64> %a, <2 x i64> %b, i32 *%ptr) { 2090 ; CHECK-LABEL: test_vchgs_all_store: 2091 ; CHECK-NOT: %r 2092 ; CHECK: vchgs %v24, %v24, %v26 2093 ; CHECK-NEXT: {{bnher|bner}} %r14 2094 ; CHECK: mvhi 0(%r2), 0 2095 ; CHECK: br %r14 2096 %call = call {<2 x i64>, i32} @llvm.s390.vchgs(<2 x i64> %a, <2 x i64> %b) 2097 %res = extractvalue {<2 x i64>, i32} %call, 0 2098 %cc = extractvalue {<2 x i64>, i32} %call, 1 2099 %cmp = icmp sle i32 %cc, 0 2100 br i1 %cmp, label %store, label %exit 2101 2102 store: 2103 store i32 0, i32 *%ptr 2104 br label %exit 2105 2106 exit: 2107 ret <2 x i64> %res 2108 } 2109 2110 ; VCHLBS with no processing of the result. 2111 define i32 @test_vchlbs(<16 x i8> %a, <16 x i8> %b) { 2112 ; CHECK-LABEL: test_vchlbs: 2113 ; CHECK: vchlbs {{%v[0-9]+}}, %v24, %v26 2114 ; CHECK: ipm %r2 2115 ; CHECK: srl %r2, 28 2116 ; CHECK: br %r14 2117 %call = call {<16 x i8>, i32} @llvm.s390.vchlbs(<16 x i8> %a, <16 x i8> %b) 2118 %res = extractvalue {<16 x i8>, i32} %call, 1 2119 ret i32 %res 2120 } 2121 2122 ; VCHLBS, returning 1 if any elements are higher (CC != 3). 2123 define i32 @test_vchlbs_any_bool(<16 x i8> %a, <16 x i8> %b) { 2124 ; CHECK-LABEL: test_vchlbs_any_bool: 2125 ; CHECK: vchlbs {{%v[0-9]+}}, %v24, %v26 2126 ; CHECK: lhi %r2, 0 2127 ; CHECK: lochile %r2, 1 2128 ; CHECK: br %r14 2129 %call = call {<16 x i8>, i32} @llvm.s390.vchlbs(<16 x i8> %a, <16 x i8> %b) 2130 %res = extractvalue {<16 x i8>, i32} %call, 1 2131 %cmp = icmp ne i32 %res, 3 2132 %ext = zext i1 %cmp to i32 2133 ret i32 %ext 2134 } 2135 2136 ; VCHLBS, storing to %ptr if any elements are higher. 2137 define <16 x i8> @test_vchlbs_any_store(<16 x i8> %a, <16 x i8> %b, i32 *%ptr) { 2138 ; CHECK-LABEL: test_vchlbs_any_store: 2139 ; CHECK-NOT: %r 2140 ; CHECK: vchlbs %v24, %v24, %v26 2141 ; CHECK-NEXT: {{bor|bnler}} %r14 2142 ; CHECK: mvhi 0(%r2), 0 2143 ; CHECK: br %r14 2144 %call = call {<16 x i8>, i32} @llvm.s390.vchlbs(<16 x i8> %a, <16 x i8> %b) 2145 %res = extractvalue {<16 x i8>, i32} %call, 0 2146 %cc = extractvalue {<16 x i8>, i32} %call, 1 2147 %cmp = icmp sle i32 %cc, 2 2148 br i1 %cmp, label %store, label %exit 2149 2150 store: 2151 store i32 0, i32 *%ptr 2152 br label %exit 2153 2154 exit: 2155 ret <16 x i8> %res 2156 } 2157 2158 ; VCHLHS with no processing of the result. 2159 define i32 @test_vchlhs(<8 x i16> %a, <8 x i16> %b) { 2160 ; CHECK-LABEL: test_vchlhs: 2161 ; CHECK: vchlhs {{%v[0-9]+}}, %v24, %v26 2162 ; CHECK: ipm %r2 2163 ; CHECK: srl %r2, 28 2164 ; CHECK: br %r14 2165 %call = call {<8 x i16>, i32} @llvm.s390.vchlhs(<8 x i16> %a, <8 x i16> %b) 2166 %res = extractvalue {<8 x i16>, i32} %call, 1 2167 ret i32 %res 2168 } 2169 2170 ; VCHLHS, returning 1 if not all elements are higher. 2171 define i32 @test_vchlhs_notall_bool(<8 x i16> %a, <8 x i16> %b) { 2172 ; CHECK-LABEL: test_vchlhs_notall_bool: 2173 ; CHECK: vchlhs {{%v[0-9]+}}, %v24, %v26 2174 ; CHECK: lhi %r2, 0 2175 ; CHECK: lochinhe %r2, 1 2176 ; CHECK: br %r14 2177 %call = call {<8 x i16>, i32} @llvm.s390.vchlhs(<8 x i16> %a, <8 x i16> %b) 2178 %res = extractvalue {<8 x i16>, i32} %call, 1 2179 %cmp = icmp uge i32 %res, 1 2180 %ext = zext i1 %cmp to i32 2181 ret i32 %ext 2182 } 2183 2184 ; VCHLHS, storing to %ptr if not all elements are higher. 2185 define <8 x i16> @test_vchlhs_notall_store(<8 x i16> %a, <8 x i16> %b, 2186 i32 *%ptr) { 2187 ; CHECK-LABEL: test_vchlhs_notall_store: 2188 ; CHECK-NOT: %r 2189 ; CHECK: vchlhs %v24, %v24, %v26 2190 ; CHECK-NEXT: {{bher|ber}} %r14 2191 ; CHECK: mvhi 0(%r2), 0 2192 ; CHECK: br %r14 2193 %call = call {<8 x i16>, i32} @llvm.s390.vchlhs(<8 x i16> %a, <8 x i16> %b) 2194 %res = extractvalue {<8 x i16>, i32} %call, 0 2195 %cc = extractvalue {<8 x i16>, i32} %call, 1 2196 %cmp = icmp sgt i32 %cc, 0 2197 br i1 %cmp, label %store, label %exit 2198 2199 store: 2200 store i32 0, i32 *%ptr 2201 br label %exit 2202 2203 exit: 2204 ret <8 x i16> %res 2205 } 2206 2207 ; VCHLFS with no processing of the result. 2208 define i32 @test_vchlfs(<4 x i32> %a, <4 x i32> %b) { 2209 ; CHECK-LABEL: test_vchlfs: 2210 ; CHECK: vchlfs {{%v[0-9]+}}, %v24, %v26 2211 ; CHECK: ipm %r2 2212 ; CHECK: srl %r2, 28 2213 ; CHECK: br %r14 2214 %call = call {<4 x i32>, i32} @llvm.s390.vchlfs(<4 x i32> %a, <4 x i32> %b) 2215 %res = extractvalue {<4 x i32>, i32} %call, 1 2216 ret i32 %res 2217 } 2218 2219 ; VCHLFS, returning 1 if no elements are higher. 2220 define i32 @test_vchlfs_none_bool(<4 x i32> %a, <4 x i32> %b) { 2221 ; CHECK-LABEL: test_vchlfs_none_bool: 2222 ; CHECK: vchlfs {{%v[0-9]+}}, %v24, %v26 2223 ; CHECK: lhi %r2, 0 2224 ; CHECK: lochio %r2, 1 2225 ; CHECK: br %r14 2226 %call = call {<4 x i32>, i32} @llvm.s390.vchlfs(<4 x i32> %a, <4 x i32> %b) 2227 %res = extractvalue {<4 x i32>, i32} %call, 1 2228 %cmp = icmp eq i32 %res, 3 2229 %ext = zext i1 %cmp to i32 2230 ret i32 %ext 2231 } 2232 2233 ; VCHLFS, storing to %ptr if no elements are higher. 2234 define <4 x i32> @test_vchlfs_none_store(<4 x i32> %a, <4 x i32> %b, 2235 i32 *%ptr) { 2236 ; CHECK-LABEL: test_vchlfs_none_store: 2237 ; CHECK-NOT: %r 2238 ; CHECK: vchlfs %v24, %v24, %v26 2239 ; CHECK-NEXT: {{bnor|bler}} %r14 2240 ; CHECK: mvhi 0(%r2), 0 2241 ; CHECK: br %r14 2242 %call = call {<4 x i32>, i32} @llvm.s390.vchlfs(<4 x i32> %a, <4 x i32> %b) 2243 %res = extractvalue {<4 x i32>, i32} %call, 0 2244 %cc = extractvalue {<4 x i32>, i32} %call, 1 2245 %cmp = icmp sge i32 %cc, 3 2246 br i1 %cmp, label %store, label %exit 2247 2248 store: 2249 store i32 0, i32 *%ptr 2250 br label %exit 2251 2252 exit: 2253 ret <4 x i32> %res 2254 } 2255 2256 ; VCHLGS with no processing of the result. 2257 define i32 @test_vchlgs(<2 x i64> %a, <2 x i64> %b) { 2258 ; CHECK-LABEL: test_vchlgs: 2259 ; CHECK: vchlgs {{%v[0-9]+}}, %v24, %v26 2260 ; CHECK: ipm %r2 2261 ; CHECK: srl %r2, 28 2262 ; CHECK: br %r14 2263 %call = call {<2 x i64>, i32} @llvm.s390.vchlgs(<2 x i64> %a, <2 x i64> %b) 2264 %res = extractvalue {<2 x i64>, i32} %call, 1 2265 ret i32 %res 2266 } 2267 2268 ; VCHLGS returning 1 if all elements are higher (CC == 0). 2269 define i32 @test_vchlgs_all_bool(<2 x i64> %a, <2 x i64> %b) { 2270 ; CHECK-LABEL: test_vchlgs_all_bool: 2271 ; CHECK: vchlgs {{%v[0-9]+}}, %v24, %v26 2272 ; CHECK: lhi %r2, 0 2273 ; CHECK: lochie %r2, 1 2274 ; CHECK: br %r14 2275 %call = call {<2 x i64>, i32} @llvm.s390.vchlgs(<2 x i64> %a, <2 x i64> %b) 2276 %res = extractvalue {<2 x i64>, i32} %call, 1 2277 %cmp = icmp slt i32 %res, 1 2278 %ext = zext i1 %cmp to i32 2279 ret i32 %ext 2280 } 2281 2282 ; VCHLGS, storing to %ptr if all elements are higher. 2283 define <2 x i64> @test_vchlgs_all_store(<2 x i64> %a, <2 x i64> %b, i32 *%ptr) { 2284 ; CHECK-LABEL: test_vchlgs_all_store: 2285 ; CHECK-NOT: %r 2286 ; CHECK: vchlgs %v24, %v24, %v26 2287 ; CHECK-NEXT: {{bnher|bner}} %r14 2288 ; CHECK: mvhi 0(%r2), 0 2289 ; CHECK: br %r14 2290 %call = call {<2 x i64>, i32} @llvm.s390.vchlgs(<2 x i64> %a, <2 x i64> %b) 2291 %res = extractvalue {<2 x i64>, i32} %call, 0 2292 %cc = extractvalue {<2 x i64>, i32} %call, 1 2293 %cmp = icmp ule i32 %cc, 0 2294 br i1 %cmp, label %store, label %exit 2295 2296 store: 2297 store i32 0, i32 *%ptr 2298 br label %exit 2299 2300 exit: 2301 ret <2 x i64> %res 2302 } 2303 2304 ; VFAEB with !IN !RT. 2305 define <16 x i8> @test_vfaeb_0(<16 x i8> %a, <16 x i8> %b) { 2306 ; CHECK-LABEL: test_vfaeb_0: 2307 ; CHECK: vfaeb %v24, %v24, %v26, 0 2308 ; CHECK: br %r14 2309 %res = call <16 x i8> @llvm.s390.vfaeb(<16 x i8> %a, <16 x i8> %b, i32 0) 2310 ret <16 x i8> %res 2311 } 2312 2313 ; VFAEB with !IN RT. 2314 define <16 x i8> @test_vfaeb_4(<16 x i8> %a, <16 x i8> %b) { 2315 ; CHECK-LABEL: test_vfaeb_4: 2316 ; CHECK: vfaeb %v24, %v24, %v26, 4 2317 ; CHECK: br %r14 2318 %res = call <16 x i8> @llvm.s390.vfaeb(<16 x i8> %a, <16 x i8> %b, i32 4) 2319 ret <16 x i8> %res 2320 } 2321 2322 ; VFAEB with IN !RT. 2323 define <16 x i8> @test_vfaeb_8(<16 x i8> %a, <16 x i8> %b) { 2324 ; CHECK-LABEL: test_vfaeb_8: 2325 ; CHECK: vfaeb %v24, %v24, %v26, 8 2326 ; CHECK: br %r14 2327 %res = call <16 x i8> @llvm.s390.vfaeb(<16 x i8> %a, <16 x i8> %b, i32 8) 2328 ret <16 x i8> %res 2329 } 2330 2331 ; VFAEB with IN RT. 2332 define <16 x i8> @test_vfaeb_12(<16 x i8> %a, <16 x i8> %b) { 2333 ; CHECK-LABEL: test_vfaeb_12: 2334 ; CHECK: vfaeb %v24, %v24, %v26, 12 2335 ; CHECK: br %r14 2336 %res = call <16 x i8> @llvm.s390.vfaeb(<16 x i8> %a, <16 x i8> %b, i32 12) 2337 ret <16 x i8> %res 2338 } 2339 2340 ; VFAEB with CS -- should be ignored. 2341 define <16 x i8> @test_vfaeb_1(<16 x i8> %a, <16 x i8> %b) { 2342 ; CHECK-LABEL: test_vfaeb_1: 2343 ; CHECK: vfaeb %v24, %v24, %v26, 0 2344 ; CHECK: br %r14 2345 %res = call <16 x i8> @llvm.s390.vfaeb(<16 x i8> %a, <16 x i8> %b, i32 1) 2346 ret <16 x i8> %res 2347 } 2348 2349 ; VFAEH. 2350 define <8 x i16> @test_vfaeh(<8 x i16> %a, <8 x i16> %b) { 2351 ; CHECK-LABEL: test_vfaeh: 2352 ; CHECK: vfaeh %v24, %v24, %v26, 4 2353 ; CHECK: br %r14 2354 %res = call <8 x i16> @llvm.s390.vfaeh(<8 x i16> %a, <8 x i16> %b, i32 4) 2355 ret <8 x i16> %res 2356 } 2357 2358 ; VFAEF. 2359 define <4 x i32> @test_vfaef(<4 x i32> %a, <4 x i32> %b) { 2360 ; CHECK-LABEL: test_vfaef: 2361 ; CHECK: vfaef %v24, %v24, %v26, 8 2362 ; CHECK: br %r14 2363 %res = call <4 x i32> @llvm.s390.vfaef(<4 x i32> %a, <4 x i32> %b, i32 8) 2364 ret <4 x i32> %res 2365 } 2366 2367 ; VFAEBS. 2368 define <16 x i8> @test_vfaebs(<16 x i8> %a, <16 x i8> %b, i32 *%ccptr) { 2369 ; CHECK-LABEL: test_vfaebs: 2370 ; CHECK: vfaebs %v24, %v24, %v26, 0 2371 ; CHECK: ipm [[REG:%r[0-5]]] 2372 ; CHECK: srl [[REG]], 28 2373 ; CHECK: st [[REG]], 0(%r2) 2374 ; CHECK: br %r14 2375 %call = call {<16 x i8>, i32} @llvm.s390.vfaebs(<16 x i8> %a, <16 x i8> %b, 2376 i32 0) 2377 %res = extractvalue {<16 x i8>, i32} %call, 0 2378 %cc = extractvalue {<16 x i8>, i32} %call, 1 2379 store i32 %cc, i32 *%ccptr 2380 ret <16 x i8> %res 2381 } 2382 2383 ; VFAEHS. 2384 define <8 x i16> @test_vfaehs(<8 x i16> %a, <8 x i16> %b, i32 *%ccptr) { 2385 ; CHECK-LABEL: test_vfaehs: 2386 ; CHECK: vfaehs %v24, %v24, %v26, 4 2387 ; CHECK: ipm [[REG:%r[0-5]]] 2388 ; CHECK: srl [[REG]], 28 2389 ; CHECK: st [[REG]], 0(%r2) 2390 ; CHECK: br %r14 2391 %call = call {<8 x i16>, i32} @llvm.s390.vfaehs(<8 x i16> %a, <8 x i16> %b, 2392 i32 4) 2393 %res = extractvalue {<8 x i16>, i32} %call, 0 2394 %cc = extractvalue {<8 x i16>, i32} %call, 1 2395 store i32 %cc, i32 *%ccptr 2396 ret <8 x i16> %res 2397 } 2398 2399 ; VFAEFS. 2400 define <4 x i32> @test_vfaefs(<4 x i32> %a, <4 x i32> %b, i32 *%ccptr) { 2401 ; CHECK-LABEL: test_vfaefs: 2402 ; CHECK: vfaefs %v24, %v24, %v26, 8 2403 ; CHECK: ipm [[REG:%r[0-5]]] 2404 ; CHECK: srl [[REG]], 28 2405 ; CHECK: st [[REG]], 0(%r2) 2406 ; CHECK: br %r14 2407 %call = call {<4 x i32>, i32} @llvm.s390.vfaefs(<4 x i32> %a, <4 x i32> %b, 2408 i32 8) 2409 %res = extractvalue {<4 x i32>, i32} %call, 0 2410 %cc = extractvalue {<4 x i32>, i32} %call, 1 2411 store i32 %cc, i32 *%ccptr 2412 ret <4 x i32> %res 2413 } 2414 2415 ; VFAEZB with !IN !RT. 2416 define <16 x i8> @test_vfaezb_0(<16 x i8> %a, <16 x i8> %b) { 2417 ; CHECK-LABEL: test_vfaezb_0: 2418 ; CHECK: vfaezb %v24, %v24, %v26, 0 2419 ; CHECK: br %r14 2420 %res = call <16 x i8> @llvm.s390.vfaezb(<16 x i8> %a, <16 x i8> %b, i32 0) 2421 ret <16 x i8> %res 2422 } 2423 2424 ; VFAEZB with !IN RT. 2425 define <16 x i8> @test_vfaezb_4(<16 x i8> %a, <16 x i8> %b) { 2426 ; CHECK-LABEL: test_vfaezb_4: 2427 ; CHECK: vfaezb %v24, %v24, %v26, 4 2428 ; CHECK: br %r14 2429 %res = call <16 x i8> @llvm.s390.vfaezb(<16 x i8> %a, <16 x i8> %b, i32 4) 2430 ret <16 x i8> %res 2431 } 2432 2433 ; VFAEZB with IN !RT. 2434 define <16 x i8> @test_vfaezb_8(<16 x i8> %a, <16 x i8> %b) { 2435 ; CHECK-LABEL: test_vfaezb_8: 2436 ; CHECK: vfaezb %v24, %v24, %v26, 8 2437 ; CHECK: br %r14 2438 %res = call <16 x i8> @llvm.s390.vfaezb(<16 x i8> %a, <16 x i8> %b, i32 8) 2439 ret <16 x i8> %res 2440 } 2441 2442 ; VFAEZB with IN RT. 2443 define <16 x i8> @test_vfaezb_12(<16 x i8> %a, <16 x i8> %b) { 2444 ; CHECK-LABEL: test_vfaezb_12: 2445 ; CHECK: vfaezb %v24, %v24, %v26, 12 2446 ; CHECK: br %r14 2447 %res = call <16 x i8> @llvm.s390.vfaezb(<16 x i8> %a, <16 x i8> %b, i32 12) 2448 ret <16 x i8> %res 2449 } 2450 2451 ; VFAEZB with CS -- should be ignored. 2452 define <16 x i8> @test_vfaezb_1(<16 x i8> %a, <16 x i8> %b) { 2453 ; CHECK-LABEL: test_vfaezb_1: 2454 ; CHECK: vfaezb %v24, %v24, %v26, 0 2455 ; CHECK: br %r14 2456 %res = call <16 x i8> @llvm.s390.vfaezb(<16 x i8> %a, <16 x i8> %b, i32 1) 2457 ret <16 x i8> %res 2458 } 2459 2460 ; VFAEZH. 2461 define <8 x i16> @test_vfaezh(<8 x i16> %a, <8 x i16> %b) { 2462 ; CHECK-LABEL: test_vfaezh: 2463 ; CHECK: vfaezh %v24, %v24, %v26, 4 2464 ; CHECK: br %r14 2465 %res = call <8 x i16> @llvm.s390.vfaezh(<8 x i16> %a, <8 x i16> %b, i32 4) 2466 ret <8 x i16> %res 2467 } 2468 2469 ; VFAEZF. 2470 define <4 x i32> @test_vfaezf(<4 x i32> %a, <4 x i32> %b) { 2471 ; CHECK-LABEL: test_vfaezf: 2472 ; CHECK: vfaezf %v24, %v24, %v26, 8 2473 ; CHECK: br %r14 2474 %res = call <4 x i32> @llvm.s390.vfaezf(<4 x i32> %a, <4 x i32> %b, i32 8) 2475 ret <4 x i32> %res 2476 } 2477 2478 ; VFAEZBS. 2479 define <16 x i8> @test_vfaezbs(<16 x i8> %a, <16 x i8> %b, i32 *%ccptr) { 2480 ; CHECK-LABEL: test_vfaezbs: 2481 ; CHECK: vfaezbs %v24, %v24, %v26, 0 2482 ; CHECK: ipm [[REG:%r[0-5]]] 2483 ; CHECK: srl [[REG]], 28 2484 ; CHECK: st [[REG]], 0(%r2) 2485 ; CHECK: br %r14 2486 %call = call {<16 x i8>, i32} @llvm.s390.vfaezbs(<16 x i8> %a, <16 x i8> %b, 2487 i32 0) 2488 %res = extractvalue {<16 x i8>, i32} %call, 0 2489 %cc = extractvalue {<16 x i8>, i32} %call, 1 2490 store i32 %cc, i32 *%ccptr 2491 ret <16 x i8> %res 2492 } 2493 2494 ; VFAEZHS. 2495 define <8 x i16> @test_vfaezhs(<8 x i16> %a, <8 x i16> %b, i32 *%ccptr) { 2496 ; CHECK-LABEL: test_vfaezhs: 2497 ; CHECK: vfaezhs %v24, %v24, %v26, 4 2498 ; CHECK: ipm [[REG:%r[0-5]]] 2499 ; CHECK: srl [[REG]], 28 2500 ; CHECK: st [[REG]], 0(%r2) 2501 ; CHECK: br %r14 2502 %call = call {<8 x i16>, i32} @llvm.s390.vfaezhs(<8 x i16> %a, <8 x i16> %b, 2503 i32 4) 2504 %res = extractvalue {<8 x i16>, i32} %call, 0 2505 %cc = extractvalue {<8 x i16>, i32} %call, 1 2506 store i32 %cc, i32 *%ccptr 2507 ret <8 x i16> %res 2508 } 2509 2510 ; VFAEZFS. 2511 define <4 x i32> @test_vfaezfs(<4 x i32> %a, <4 x i32> %b, i32 *%ccptr) { 2512 ; CHECK-LABEL: test_vfaezfs: 2513 ; CHECK: vfaezfs %v24, %v24, %v26, 8 2514 ; CHECK: ipm [[REG:%r[0-5]]] 2515 ; CHECK: srl [[REG]], 28 2516 ; CHECK: st [[REG]], 0(%r2) 2517 ; CHECK: br %r14 2518 %call = call {<4 x i32>, i32} @llvm.s390.vfaezfs(<4 x i32> %a, <4 x i32> %b, 2519 i32 8) 2520 %res = extractvalue {<4 x i32>, i32} %call, 0 2521 %cc = extractvalue {<4 x i32>, i32} %call, 1 2522 store i32 %cc, i32 *%ccptr 2523 ret <4 x i32> %res 2524 } 2525 2526 ; VFEEB. 2527 define <16 x i8> @test_vfeeb_0(<16 x i8> %a, <16 x i8> %b) { 2528 ; CHECK-LABEL: test_vfeeb_0: 2529 ; CHECK: vfeeb %v24, %v24, %v26 2530 ; CHECK: br %r14 2531 %res = call <16 x i8> @llvm.s390.vfeeb(<16 x i8> %a, <16 x i8> %b) 2532 ret <16 x i8> %res 2533 } 2534 2535 ; VFEEH. 2536 define <8 x i16> @test_vfeeh(<8 x i16> %a, <8 x i16> %b) { 2537 ; CHECK-LABEL: test_vfeeh: 2538 ; CHECK: vfeeh %v24, %v24, %v26 2539 ; CHECK: br %r14 2540 %res = call <8 x i16> @llvm.s390.vfeeh(<8 x i16> %a, <8 x i16> %b) 2541 ret <8 x i16> %res 2542 } 2543 2544 ; VFEEF. 2545 define <4 x i32> @test_vfeef(<4 x i32> %a, <4 x i32> %b) { 2546 ; CHECK-LABEL: test_vfeef: 2547 ; CHECK: vfeef %v24, %v24, %v26 2548 ; CHECK: br %r14 2549 %res = call <4 x i32> @llvm.s390.vfeef(<4 x i32> %a, <4 x i32> %b) 2550 ret <4 x i32> %res 2551 } 2552 2553 ; VFEEBS. 2554 define <16 x i8> @test_vfeebs(<16 x i8> %a, <16 x i8> %b, i32 *%ccptr) { 2555 ; CHECK-LABEL: test_vfeebs: 2556 ; CHECK: vfeebs %v24, %v24, %v26 2557 ; CHECK: ipm [[REG:%r[0-5]]] 2558 ; CHECK: srl [[REG]], 28 2559 ; CHECK: st [[REG]], 0(%r2) 2560 ; CHECK: br %r14 2561 %call = call {<16 x i8>, i32} @llvm.s390.vfeebs(<16 x i8> %a, <16 x i8> %b) 2562 %res = extractvalue {<16 x i8>, i32} %call, 0 2563 %cc = extractvalue {<16 x i8>, i32} %call, 1 2564 store i32 %cc, i32 *%ccptr 2565 ret <16 x i8> %res 2566 } 2567 2568 ; VFEEHS. 2569 define <8 x i16> @test_vfeehs(<8 x i16> %a, <8 x i16> %b, i32 *%ccptr) { 2570 ; CHECK-LABEL: test_vfeehs: 2571 ; CHECK: vfeehs %v24, %v24, %v26 2572 ; CHECK: ipm [[REG:%r[0-5]]] 2573 ; CHECK: srl [[REG]], 28 2574 ; CHECK: st [[REG]], 0(%r2) 2575 ; CHECK: br %r14 2576 %call = call {<8 x i16>, i32} @llvm.s390.vfeehs(<8 x i16> %a, <8 x i16> %b) 2577 %res = extractvalue {<8 x i16>, i32} %call, 0 2578 %cc = extractvalue {<8 x i16>, i32} %call, 1 2579 store i32 %cc, i32 *%ccptr 2580 ret <8 x i16> %res 2581 } 2582 2583 ; VFEEFS. 2584 define <4 x i32> @test_vfeefs(<4 x i32> %a, <4 x i32> %b, i32 *%ccptr) { 2585 ; CHECK-LABEL: test_vfeefs: 2586 ; CHECK: vfeefs %v24, %v24, %v26 2587 ; CHECK: ipm [[REG:%r[0-5]]] 2588 ; CHECK: srl [[REG]], 28 2589 ; CHECK: st [[REG]], 0(%r2) 2590 ; CHECK: br %r14 2591 %call = call {<4 x i32>, i32} @llvm.s390.vfeefs(<4 x i32> %a, <4 x i32> %b) 2592 %res = extractvalue {<4 x i32>, i32} %call, 0 2593 %cc = extractvalue {<4 x i32>, i32} %call, 1 2594 store i32 %cc, i32 *%ccptr 2595 ret <4 x i32> %res 2596 } 2597 2598 ; VFEEZB. 2599 define <16 x i8> @test_vfeezb(<16 x i8> %a, <16 x i8> %b) { 2600 ; CHECK-LABEL: test_vfeezb: 2601 ; CHECK: vfeezb %v24, %v24, %v26 2602 ; CHECK: br %r14 2603 %res = call <16 x i8> @llvm.s390.vfeezb(<16 x i8> %a, <16 x i8> %b) 2604 ret <16 x i8> %res 2605 } 2606 2607 ; VFEEZH. 2608 define <8 x i16> @test_vfeezh(<8 x i16> %a, <8 x i16> %b) { 2609 ; CHECK-LABEL: test_vfeezh: 2610 ; CHECK: vfeezh %v24, %v24, %v26 2611 ; CHECK: br %r14 2612 %res = call <8 x i16> @llvm.s390.vfeezh(<8 x i16> %a, <8 x i16> %b) 2613 ret <8 x i16> %res 2614 } 2615 2616 ; VFEEZF. 2617 define <4 x i32> @test_vfeezf(<4 x i32> %a, <4 x i32> %b) { 2618 ; CHECK-LABEL: test_vfeezf: 2619 ; CHECK: vfeezf %v24, %v24, %v26 2620 ; CHECK: br %r14 2621 %res = call <4 x i32> @llvm.s390.vfeezf(<4 x i32> %a, <4 x i32> %b) 2622 ret <4 x i32> %res 2623 } 2624 2625 ; VFEEZBS. 2626 define <16 x i8> @test_vfeezbs(<16 x i8> %a, <16 x i8> %b, i32 *%ccptr) { 2627 ; CHECK-LABEL: test_vfeezbs: 2628 ; CHECK: vfeezbs %v24, %v24, %v26 2629 ; CHECK: ipm [[REG:%r[0-5]]] 2630 ; CHECK: srl [[REG]], 28 2631 ; CHECK: st [[REG]], 0(%r2) 2632 ; CHECK: br %r14 2633 %call = call {<16 x i8>, i32} @llvm.s390.vfeezbs(<16 x i8> %a, <16 x i8> %b) 2634 %res = extractvalue {<16 x i8>, i32} %call, 0 2635 %cc = extractvalue {<16 x i8>, i32} %call, 1 2636 store i32 %cc, i32 *%ccptr 2637 ret <16 x i8> %res 2638 } 2639 2640 ; VFEEZHS. 2641 define <8 x i16> @test_vfeezhs(<8 x i16> %a, <8 x i16> %b, i32 *%ccptr) { 2642 ; CHECK-LABEL: test_vfeezhs: 2643 ; CHECK: vfeezhs %v24, %v24, %v26 2644 ; CHECK: ipm [[REG:%r[0-5]]] 2645 ; CHECK: srl [[REG]], 28 2646 ; CHECK: st [[REG]], 0(%r2) 2647 ; CHECK: br %r14 2648 %call = call {<8 x i16>, i32} @llvm.s390.vfeezhs(<8 x i16> %a, <8 x i16> %b) 2649 %res = extractvalue {<8 x i16>, i32} %call, 0 2650 %cc = extractvalue {<8 x i16>, i32} %call, 1 2651 store i32 %cc, i32 *%ccptr 2652 ret <8 x i16> %res 2653 } 2654 2655 ; VFEEZFS. 2656 define <4 x i32> @test_vfeezfs(<4 x i32> %a, <4 x i32> %b, i32 *%ccptr) { 2657 ; CHECK-LABEL: test_vfeezfs: 2658 ; CHECK: vfeezfs %v24, %v24, %v26 2659 ; CHECK: ipm [[REG:%r[0-5]]] 2660 ; CHECK: srl [[REG]], 28 2661 ; CHECK: st [[REG]], 0(%r2) 2662 ; CHECK: br %r14 2663 %call = call {<4 x i32>, i32} @llvm.s390.vfeezfs(<4 x i32> %a, <4 x i32> %b) 2664 %res = extractvalue {<4 x i32>, i32} %call, 0 2665 %cc = extractvalue {<4 x i32>, i32} %call, 1 2666 store i32 %cc, i32 *%ccptr 2667 ret <4 x i32> %res 2668 } 2669 2670 ; VFENEB. 2671 define <16 x i8> @test_vfeneb_0(<16 x i8> %a, <16 x i8> %b) { 2672 ; CHECK-LABEL: test_vfeneb_0: 2673 ; CHECK: vfeneb %v24, %v24, %v26 2674 ; CHECK: br %r14 2675 %res = call <16 x i8> @llvm.s390.vfeneb(<16 x i8> %a, <16 x i8> %b) 2676 ret <16 x i8> %res 2677 } 2678 2679 ; VFENEH. 2680 define <8 x i16> @test_vfeneh(<8 x i16> %a, <8 x i16> %b) { 2681 ; CHECK-LABEL: test_vfeneh: 2682 ; CHECK: vfeneh %v24, %v24, %v26 2683 ; CHECK: br %r14 2684 %res = call <8 x i16> @llvm.s390.vfeneh(<8 x i16> %a, <8 x i16> %b) 2685 ret <8 x i16> %res 2686 } 2687 2688 ; VFENEF. 2689 define <4 x i32> @test_vfenef(<4 x i32> %a, <4 x i32> %b) { 2690 ; CHECK-LABEL: test_vfenef: 2691 ; CHECK: vfenef %v24, %v24, %v26 2692 ; CHECK: br %r14 2693 %res = call <4 x i32> @llvm.s390.vfenef(<4 x i32> %a, <4 x i32> %b) 2694 ret <4 x i32> %res 2695 } 2696 2697 ; VFENEBS. 2698 define <16 x i8> @test_vfenebs(<16 x i8> %a, <16 x i8> %b, i32 *%ccptr) { 2699 ; CHECK-LABEL: test_vfenebs: 2700 ; CHECK: vfenebs %v24, %v24, %v26 2701 ; CHECK: ipm [[REG:%r[0-5]]] 2702 ; CHECK: srl [[REG]], 28 2703 ; CHECK: st [[REG]], 0(%r2) 2704 ; CHECK: br %r14 2705 %call = call {<16 x i8>, i32} @llvm.s390.vfenebs(<16 x i8> %a, <16 x i8> %b) 2706 %res = extractvalue {<16 x i8>, i32} %call, 0 2707 %cc = extractvalue {<16 x i8>, i32} %call, 1 2708 store i32 %cc, i32 *%ccptr 2709 ret <16 x i8> %res 2710 } 2711 2712 ; VFENEHS. 2713 define <8 x i16> @test_vfenehs(<8 x i16> %a, <8 x i16> %b, i32 *%ccptr) { 2714 ; CHECK-LABEL: test_vfenehs: 2715 ; CHECK: vfenehs %v24, %v24, %v26 2716 ; CHECK: ipm [[REG:%r[0-5]]] 2717 ; CHECK: srl [[REG]], 28 2718 ; CHECK: st [[REG]], 0(%r2) 2719 ; CHECK: br %r14 2720 %call = call {<8 x i16>, i32} @llvm.s390.vfenehs(<8 x i16> %a, <8 x i16> %b) 2721 %res = extractvalue {<8 x i16>, i32} %call, 0 2722 %cc = extractvalue {<8 x i16>, i32} %call, 1 2723 store i32 %cc, i32 *%ccptr 2724 ret <8 x i16> %res 2725 } 2726 2727 ; VFENEFS. 2728 define <4 x i32> @test_vfenefs(<4 x i32> %a, <4 x i32> %b, i32 *%ccptr) { 2729 ; CHECK-LABEL: test_vfenefs: 2730 ; CHECK: vfenefs %v24, %v24, %v26 2731 ; CHECK: ipm [[REG:%r[0-5]]] 2732 ; CHECK: srl [[REG]], 28 2733 ; CHECK: st [[REG]], 0(%r2) 2734 ; CHECK: br %r14 2735 %call = call {<4 x i32>, i32} @llvm.s390.vfenefs(<4 x i32> %a, <4 x i32> %b) 2736 %res = extractvalue {<4 x i32>, i32} %call, 0 2737 %cc = extractvalue {<4 x i32>, i32} %call, 1 2738 store i32 %cc, i32 *%ccptr 2739 ret <4 x i32> %res 2740 } 2741 2742 ; VFENEZB. 2743 define <16 x i8> @test_vfenezb(<16 x i8> %a, <16 x i8> %b) { 2744 ; CHECK-LABEL: test_vfenezb: 2745 ; CHECK: vfenezb %v24, %v24, %v26 2746 ; CHECK: br %r14 2747 %res = call <16 x i8> @llvm.s390.vfenezb(<16 x i8> %a, <16 x i8> %b) 2748 ret <16 x i8> %res 2749 } 2750 2751 ; VFENEZH. 2752 define <8 x i16> @test_vfenezh(<8 x i16> %a, <8 x i16> %b) { 2753 ; CHECK-LABEL: test_vfenezh: 2754 ; CHECK: vfenezh %v24, %v24, %v26 2755 ; CHECK: br %r14 2756 %res = call <8 x i16> @llvm.s390.vfenezh(<8 x i16> %a, <8 x i16> %b) 2757 ret <8 x i16> %res 2758 } 2759 2760 ; VFENEZF. 2761 define <4 x i32> @test_vfenezf(<4 x i32> %a, <4 x i32> %b) { 2762 ; CHECK-LABEL: test_vfenezf: 2763 ; CHECK: vfenezf %v24, %v24, %v26 2764 ; CHECK: br %r14 2765 %res = call <4 x i32> @llvm.s390.vfenezf(<4 x i32> %a, <4 x i32> %b) 2766 ret <4 x i32> %res 2767 } 2768 2769 ; VFENEZBS. 2770 define <16 x i8> @test_vfenezbs(<16 x i8> %a, <16 x i8> %b, i32 *%ccptr) { 2771 ; CHECK-LABEL: test_vfenezbs: 2772 ; CHECK: vfenezbs %v24, %v24, %v26 2773 ; CHECK: ipm [[REG:%r[0-5]]] 2774 ; CHECK: srl [[REG]], 28 2775 ; CHECK: st [[REG]], 0(%r2) 2776 ; CHECK: br %r14 2777 %call = call {<16 x i8>, i32} @llvm.s390.vfenezbs(<16 x i8> %a, <16 x i8> %b) 2778 %res = extractvalue {<16 x i8>, i32} %call, 0 2779 %cc = extractvalue {<16 x i8>, i32} %call, 1 2780 store i32 %cc, i32 *%ccptr 2781 ret <16 x i8> %res 2782 } 2783 2784 ; VFENEZHS. 2785 define <8 x i16> @test_vfenezhs(<8 x i16> %a, <8 x i16> %b, i32 *%ccptr) { 2786 ; CHECK-LABEL: test_vfenezhs: 2787 ; CHECK: vfenezhs %v24, %v24, %v26 2788 ; CHECK: ipm [[REG:%r[0-5]]] 2789 ; CHECK: srl [[REG]], 28 2790 ; CHECK: st [[REG]], 0(%r2) 2791 ; CHECK: br %r14 2792 %call = call {<8 x i16>, i32} @llvm.s390.vfenezhs(<8 x i16> %a, <8 x i16> %b) 2793 %res = extractvalue {<8 x i16>, i32} %call, 0 2794 %cc = extractvalue {<8 x i16>, i32} %call, 1 2795 store i32 %cc, i32 *%ccptr 2796 ret <8 x i16> %res 2797 } 2798 2799 ; VFENEZFS. 2800 define <4 x i32> @test_vfenezfs(<4 x i32> %a, <4 x i32> %b, i32 *%ccptr) { 2801 ; CHECK-LABEL: test_vfenezfs: 2802 ; CHECK: vfenezfs %v24, %v24, %v26 2803 ; CHECK: ipm [[REG:%r[0-5]]] 2804 ; CHECK: srl [[REG]], 28 2805 ; CHECK: st [[REG]], 0(%r2) 2806 ; CHECK: br %r14 2807 %call = call {<4 x i32>, i32} @llvm.s390.vfenezfs(<4 x i32> %a, <4 x i32> %b) 2808 %res = extractvalue {<4 x i32>, i32} %call, 0 2809 %cc = extractvalue {<4 x i32>, i32} %call, 1 2810 store i32 %cc, i32 *%ccptr 2811 ret <4 x i32> %res 2812 } 2813 2814 ; VISTRB. 2815 define <16 x i8> @test_vistrb(<16 x i8> %a) { 2816 ; CHECK-LABEL: test_vistrb: 2817 ; CHECK: vistrb %v24, %v24 2818 ; CHECK: br %r14 2819 %res = call <16 x i8> @llvm.s390.vistrb(<16 x i8> %a) 2820 ret <16 x i8> %res 2821 } 2822 2823 ; VISTRH. 2824 define <8 x i16> @test_vistrh(<8 x i16> %a) { 2825 ; CHECK-LABEL: test_vistrh: 2826 ; CHECK: vistrh %v24, %v24 2827 ; CHECK: br %r14 2828 %res = call <8 x i16> @llvm.s390.vistrh(<8 x i16> %a) 2829 ret <8 x i16> %res 2830 } 2831 2832 ; VISTRF. 2833 define <4 x i32> @test_vistrf(<4 x i32> %a) { 2834 ; CHECK-LABEL: test_vistrf: 2835 ; CHECK: vistrf %v24, %v24 2836 ; CHECK: br %r14 2837 %res = call <4 x i32> @llvm.s390.vistrf(<4 x i32> %a) 2838 ret <4 x i32> %res 2839 } 2840 2841 ; VISTRBS. 2842 define <16 x i8> @test_vistrbs(<16 x i8> %a, i32 *%ccptr) { 2843 ; CHECK-LABEL: test_vistrbs: 2844 ; CHECK: vistrbs %v24, %v24 2845 ; CHECK: ipm [[REG:%r[0-5]]] 2846 ; CHECK: srl [[REG]], 28 2847 ; CHECK: st [[REG]], 0(%r2) 2848 ; CHECK: br %r14 2849 %call = call {<16 x i8>, i32} @llvm.s390.vistrbs(<16 x i8> %a) 2850 %res = extractvalue {<16 x i8>, i32} %call, 0 2851 %cc = extractvalue {<16 x i8>, i32} %call, 1 2852 store i32 %cc, i32 *%ccptr 2853 ret <16 x i8> %res 2854 } 2855 2856 ; VISTRHS. 2857 define <8 x i16> @test_vistrhs(<8 x i16> %a, i32 *%ccptr) { 2858 ; CHECK-LABEL: test_vistrhs: 2859 ; CHECK: vistrhs %v24, %v24 2860 ; CHECK: ipm [[REG:%r[0-5]]] 2861 ; CHECK: srl [[REG]], 28 2862 ; CHECK: st [[REG]], 0(%r2) 2863 ; CHECK: br %r14 2864 %call = call {<8 x i16>, i32} @llvm.s390.vistrhs(<8 x i16> %a) 2865 %res = extractvalue {<8 x i16>, i32} %call, 0 2866 %cc = extractvalue {<8 x i16>, i32} %call, 1 2867 store i32 %cc, i32 *%ccptr 2868 ret <8 x i16> %res 2869 } 2870 2871 ; VISTRFS. 2872 define <4 x i32> @test_vistrfs(<4 x i32> %a, i32 *%ccptr) { 2873 ; CHECK-LABEL: test_vistrfs: 2874 ; CHECK: vistrfs %v24, %v24 2875 ; CHECK: ipm [[REG:%r[0-5]]] 2876 ; CHECK: srl [[REG]], 28 2877 ; CHECK: st [[REG]], 0(%r2) 2878 ; CHECK: br %r14 2879 %call = call {<4 x i32>, i32} @llvm.s390.vistrfs(<4 x i32> %a) 2880 %res = extractvalue {<4 x i32>, i32} %call, 0 2881 %cc = extractvalue {<4 x i32>, i32} %call, 1 2882 store i32 %cc, i32 *%ccptr 2883 ret <4 x i32> %res 2884 } 2885 2886 ; VSTRCB with !IN !RT. 2887 define <16 x i8> @test_vstrcb_0(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) { 2888 ; CHECK-LABEL: test_vstrcb_0: 2889 ; CHECK: vstrcb %v24, %v24, %v26, %v28, 0 2890 ; CHECK: br %r14 2891 %res = call <16 x i8> @llvm.s390.vstrcb(<16 x i8> %a, <16 x i8> %b, 2892 <16 x i8> %c, i32 0) 2893 ret <16 x i8> %res 2894 } 2895 2896 ; VSTRCB with !IN RT. 2897 define <16 x i8> @test_vstrcb_4(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) { 2898 ; CHECK-LABEL: test_vstrcb_4: 2899 ; CHECK: vstrcb %v24, %v24, %v26, %v28, 4 2900 ; CHECK: br %r14 2901 %res = call <16 x i8> @llvm.s390.vstrcb(<16 x i8> %a, <16 x i8> %b, 2902 <16 x i8> %c, i32 4) 2903 ret <16 x i8> %res 2904 } 2905 2906 ; VSTRCB with IN !RT. 2907 define <16 x i8> @test_vstrcb_8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) { 2908 ; CHECK-LABEL: test_vstrcb_8: 2909 ; CHECK: vstrcb %v24, %v24, %v26, %v28, 8 2910 ; CHECK: br %r14 2911 %res = call <16 x i8> @llvm.s390.vstrcb(<16 x i8> %a, <16 x i8> %b, 2912 <16 x i8> %c, i32 8) 2913 ret <16 x i8> %res 2914 } 2915 2916 ; VSTRCB with IN RT. 2917 define <16 x i8> @test_vstrcb_12(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) { 2918 ; CHECK-LABEL: test_vstrcb_12: 2919 ; CHECK: vstrcb %v24, %v24, %v26, %v28, 12 2920 ; CHECK: br %r14 2921 %res = call <16 x i8> @llvm.s390.vstrcb(<16 x i8> %a, <16 x i8> %b, 2922 <16 x i8> %c, i32 12) 2923 ret <16 x i8> %res 2924 } 2925 2926 ; VSTRCB with CS -- should be ignored. 2927 define <16 x i8> @test_vstrcb_1(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) { 2928 ; CHECK-LABEL: test_vstrcb_1: 2929 ; CHECK: vstrcb %v24, %v24, %v26, %v28, 0 2930 ; CHECK: br %r14 2931 %res = call <16 x i8> @llvm.s390.vstrcb(<16 x i8> %a, <16 x i8> %b, 2932 <16 x i8> %c, i32 1) 2933 ret <16 x i8> %res 2934 } 2935 2936 ; VSTRCH. 2937 define <8 x i16> @test_vstrch(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) { 2938 ; CHECK-LABEL: test_vstrch: 2939 ; CHECK: vstrch %v24, %v24, %v26, %v28, 4 2940 ; CHECK: br %r14 2941 %res = call <8 x i16> @llvm.s390.vstrch(<8 x i16> %a, <8 x i16> %b, 2942 <8 x i16> %c, i32 4) 2943 ret <8 x i16> %res 2944 } 2945 2946 ; VSTRCF. 2947 define <4 x i32> @test_vstrcf(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) { 2948 ; CHECK-LABEL: test_vstrcf: 2949 ; CHECK: vstrcf %v24, %v24, %v26, %v28, 8 2950 ; CHECK: br %r14 2951 %res = call <4 x i32> @llvm.s390.vstrcf(<4 x i32> %a, <4 x i32> %b, 2952 <4 x i32> %c, i32 8) 2953 ret <4 x i32> %res 2954 } 2955 2956 ; VSTRCBS. 2957 define <16 x i8> @test_vstrcbs(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c, 2958 i32 *%ccptr) { 2959 ; CHECK-LABEL: test_vstrcbs: 2960 ; CHECK: vstrcbs %v24, %v24, %v26, %v28, 0 2961 ; CHECK: ipm [[REG:%r[0-5]]] 2962 ; CHECK: srl [[REG]], 28 2963 ; CHECK: st [[REG]], 0(%r2) 2964 ; CHECK: br %r14 2965 %call = call {<16 x i8>, i32} @llvm.s390.vstrcbs(<16 x i8> %a, <16 x i8> %b, 2966 <16 x i8> %c, i32 0) 2967 %res = extractvalue {<16 x i8>, i32} %call, 0 2968 %cc = extractvalue {<16 x i8>, i32} %call, 1 2969 store i32 %cc, i32 *%ccptr 2970 ret <16 x i8> %res 2971 } 2972 2973 ; VSTRCHS. 2974 define <8 x i16> @test_vstrchs(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c, 2975 i32 *%ccptr) { 2976 ; CHECK-LABEL: test_vstrchs: 2977 ; CHECK: vstrchs %v24, %v24, %v26, %v28, 4 2978 ; CHECK: ipm [[REG:%r[0-5]]] 2979 ; CHECK: srl [[REG]], 28 2980 ; CHECK: st [[REG]], 0(%r2) 2981 ; CHECK: br %r14 2982 %call = call {<8 x i16>, i32} @llvm.s390.vstrchs(<8 x i16> %a, <8 x i16> %b, 2983 <8 x i16> %c, i32 4) 2984 %res = extractvalue {<8 x i16>, i32} %call, 0 2985 %cc = extractvalue {<8 x i16>, i32} %call, 1 2986 store i32 %cc, i32 *%ccptr 2987 ret <8 x i16> %res 2988 } 2989 2990 ; VSTRCFS. 2991 define <4 x i32> @test_vstrcfs(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, 2992 i32 *%ccptr) { 2993 ; CHECK-LABEL: test_vstrcfs: 2994 ; CHECK: vstrcfs %v24, %v24, %v26, %v28, 8 2995 ; CHECK: ipm [[REG:%r[0-5]]] 2996 ; CHECK: srl [[REG]], 28 2997 ; CHECK: st [[REG]], 0(%r2) 2998 ; CHECK: br %r14 2999 %call = call {<4 x i32>, i32} @llvm.s390.vstrcfs(<4 x i32> %a, <4 x i32> %b, 3000 <4 x i32> %c, i32 8) 3001 %res = extractvalue {<4 x i32>, i32} %call, 0 3002 %cc = extractvalue {<4 x i32>, i32} %call, 1 3003 store i32 %cc, i32 *%ccptr 3004 ret <4 x i32> %res 3005 } 3006 3007 ; VSTRCZB with !IN !RT. 3008 define <16 x i8> @test_vstrczb_0(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) { 3009 ; CHECK-LABEL: test_vstrczb_0: 3010 ; CHECK: vstrczb %v24, %v24, %v26, %v28, 0 3011 ; CHECK: br %r14 3012 %res = call <16 x i8> @llvm.s390.vstrczb(<16 x i8> %a, <16 x i8> %b, 3013 <16 x i8> %c, i32 0) 3014 ret <16 x i8> %res 3015 } 3016 3017 ; VSTRCZB with !IN RT. 3018 define <16 x i8> @test_vstrczb_4(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) { 3019 ; CHECK-LABEL: test_vstrczb_4: 3020 ; CHECK: vstrczb %v24, %v24, %v26, %v28, 4 3021 ; CHECK: br %r14 3022 %res = call <16 x i8> @llvm.s390.vstrczb(<16 x i8> %a, <16 x i8> %b, 3023 <16 x i8> %c, i32 4) 3024 ret <16 x i8> %res 3025 } 3026 3027 ; VSTRCZB with IN !RT. 3028 define <16 x i8> @test_vstrczb_8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) { 3029 ; CHECK-LABEL: test_vstrczb_8: 3030 ; CHECK: vstrczb %v24, %v24, %v26, %v28, 8 3031 ; CHECK: br %r14 3032 %res = call <16 x i8> @llvm.s390.vstrczb(<16 x i8> %a, <16 x i8> %b, 3033 <16 x i8> %c, i32 8) 3034 ret <16 x i8> %res 3035 } 3036 3037 ; VSTRCZB with IN RT. 3038 define <16 x i8> @test_vstrczb_12(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) { 3039 ; CHECK-LABEL: test_vstrczb_12: 3040 ; CHECK: vstrczb %v24, %v24, %v26, %v28, 12 3041 ; CHECK: br %r14 3042 %res = call <16 x i8> @llvm.s390.vstrczb(<16 x i8> %a, <16 x i8> %b, 3043 <16 x i8> %c, i32 12) 3044 ret <16 x i8> %res 3045 } 3046 3047 ; VSTRCZB with CS -- should be ignored. 3048 define <16 x i8> @test_vstrczb_1(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) { 3049 ; CHECK-LABEL: test_vstrczb_1: 3050 ; CHECK: vstrczb %v24, %v24, %v26, %v28, 0 3051 ; CHECK: br %r14 3052 %res = call <16 x i8> @llvm.s390.vstrczb(<16 x i8> %a, <16 x i8> %b, 3053 <16 x i8> %c, i32 1) 3054 ret <16 x i8> %res 3055 } 3056 3057 ; VSTRCZH. 3058 define <8 x i16> @test_vstrczh(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) { 3059 ; CHECK-LABEL: test_vstrczh: 3060 ; CHECK: vstrczh %v24, %v24, %v26, %v28, 4 3061 ; CHECK: br %r14 3062 %res = call <8 x i16> @llvm.s390.vstrczh(<8 x i16> %a, <8 x i16> %b, 3063 <8 x i16> %c, i32 4) 3064 ret <8 x i16> %res 3065 } 3066 3067 ; VSTRCZF. 3068 define <4 x i32> @test_vstrczf(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) { 3069 ; CHECK-LABEL: test_vstrczf: 3070 ; CHECK: vstrczf %v24, %v24, %v26, %v28, 8 3071 ; CHECK: br %r14 3072 %res = call <4 x i32> @llvm.s390.vstrczf(<4 x i32> %a, <4 x i32> %b, 3073 <4 x i32> %c, i32 8) 3074 ret <4 x i32> %res 3075 } 3076 3077 ; VSTRCZBS. 3078 define <16 x i8> @test_vstrczbs(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c, 3079 i32 *%ccptr) { 3080 ; CHECK-LABEL: test_vstrczbs: 3081 ; CHECK: vstrczbs %v24, %v24, %v26, %v28, 0 3082 ; CHECK: ipm [[REG:%r[0-5]]] 3083 ; CHECK: srl [[REG]], 28 3084 ; CHECK: st [[REG]], 0(%r2) 3085 ; CHECK: br %r14 3086 %call = call {<16 x i8>, i32} @llvm.s390.vstrczbs(<16 x i8> %a, <16 x i8> %b, 3087 <16 x i8> %c, i32 0) 3088 %res = extractvalue {<16 x i8>, i32} %call, 0 3089 %cc = extractvalue {<16 x i8>, i32} %call, 1 3090 store i32 %cc, i32 *%ccptr 3091 ret <16 x i8> %res 3092 } 3093 3094 ; VSTRCZHS. 3095 define <8 x i16> @test_vstrczhs(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c, 3096 i32 *%ccptr) { 3097 ; CHECK-LABEL: test_vstrczhs: 3098 ; CHECK: vstrczhs %v24, %v24, %v26, %v28, 4 3099 ; CHECK: ipm [[REG:%r[0-5]]] 3100 ; CHECK: srl [[REG]], 28 3101 ; CHECK: st [[REG]], 0(%r2) 3102 ; CHECK: br %r14 3103 %call = call {<8 x i16>, i32} @llvm.s390.vstrczhs(<8 x i16> %a, <8 x i16> %b, 3104 <8 x i16> %c, i32 4) 3105 %res = extractvalue {<8 x i16>, i32} %call, 0 3106 %cc = extractvalue {<8 x i16>, i32} %call, 1 3107 store i32 %cc, i32 *%ccptr 3108 ret <8 x i16> %res 3109 } 3110 3111 ; VSTRCZFS. 3112 define <4 x i32> @test_vstrczfs(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, 3113 i32 *%ccptr) { 3114 ; CHECK-LABEL: test_vstrczfs: 3115 ; CHECK: vstrczfs %v24, %v24, %v26, %v28, 8 3116 ; CHECK: ipm [[REG:%r[0-5]]] 3117 ; CHECK: srl [[REG]], 28 3118 ; CHECK: st [[REG]], 0(%r2) 3119 ; CHECK: br %r14 3120 %call = call {<4 x i32>, i32} @llvm.s390.vstrczfs(<4 x i32> %a, <4 x i32> %b, 3121 <4 x i32> %c, i32 8) 3122 %res = extractvalue {<4 x i32>, i32} %call, 0 3123 %cc = extractvalue {<4 x i32>, i32} %call, 1 3124 store i32 %cc, i32 *%ccptr 3125 ret <4 x i32> %res 3126 } 3127 3128 ; VFCEDBS with no processing of the result. 3129 define i32 @test_vfcedbs(<2 x double> %a, <2 x double> %b) { 3130 ; CHECK-LABEL: test_vfcedbs: 3131 ; CHECK: vfcedbs {{%v[0-9]+}}, %v24, %v26 3132 ; CHECK: ipm %r2 3133 ; CHECK: srl %r2, 28 3134 ; CHECK: br %r14 3135 %call = call {<2 x i64>, i32} @llvm.s390.vfcedbs(<2 x double> %a, 3136 <2 x double> %b) 3137 %res = extractvalue {<2 x i64>, i32} %call, 1 3138 ret i32 %res 3139 } 3140 3141 ; VFCEDBS, returning 1 if any elements are equal (CC != 3). 3142 define i32 @test_vfcedbs_any_bool(<2 x double> %a, <2 x double> %b) { 3143 ; CHECK-LABEL: test_vfcedbs_any_bool: 3144 ; CHECK: vfcedbs {{%v[0-9]+}}, %v24, %v26 3145 ; CHECK: lhi %r2, 0 3146 ; CHECK: lochile %r2, 1 3147 ; CHECK: br %r14 3148 %call = call {<2 x i64>, i32} @llvm.s390.vfcedbs(<2 x double> %a, 3149 <2 x double> %b) 3150 %res = extractvalue {<2 x i64>, i32} %call, 1 3151 %cmp = icmp ne i32 %res, 3 3152 %ext = zext i1 %cmp to i32 3153 ret i32 %ext 3154 } 3155 3156 ; VFCEDBS, storing to %ptr if any elements are equal. 3157 define <2 x i64> @test_vfcedbs_any_store(<2 x double> %a, <2 x double> %b, 3158 i32 *%ptr) { 3159 ; CHECK-LABEL: test_vfcedbs_any_store: 3160 ; CHECK-NOT: %r 3161 ; CHECK: vfcedbs %v24, %v24, %v26 3162 ; CHECK-NEXT: {{bor|bnler}} %r14 3163 ; CHECK: mvhi 0(%r2), 0 3164 ; CHECK: br %r14 3165 %call = call {<2 x i64>, i32} @llvm.s390.vfcedbs(<2 x double> %a, 3166 <2 x double> %b) 3167 %res = extractvalue {<2 x i64>, i32} %call, 0 3168 %cc = extractvalue {<2 x i64>, i32} %call, 1 3169 %cmp = icmp ule i32 %cc, 2 3170 br i1 %cmp, label %store, label %exit 3171 3172 store: 3173 store i32 0, i32 *%ptr 3174 br label %exit 3175 3176 exit: 3177 ret <2 x i64> %res 3178 } 3179 3180 ; VFCHDBS with no processing of the result. 3181 define i32 @test_vfchdbs(<2 x double> %a, <2 x double> %b) { 3182 ; CHECK-LABEL: test_vfchdbs: 3183 ; CHECK: vfchdbs {{%v[0-9]+}}, %v24, %v26 3184 ; CHECK: ipm %r2 3185 ; CHECK: srl %r2, 28 3186 ; CHECK: br %r14 3187 %call = call {<2 x i64>, i32} @llvm.s390.vfchdbs(<2 x double> %a, 3188 <2 x double> %b) 3189 %res = extractvalue {<2 x i64>, i32} %call, 1 3190 ret i32 %res 3191 } 3192 3193 ; VFCHDBS, returning 1 if not all elements are higher. 3194 define i32 @test_vfchdbs_notall_bool(<2 x double> %a, <2 x double> %b) { 3195 ; CHECK-LABEL: test_vfchdbs_notall_bool: 3196 ; CHECK: vfchdbs {{%v[0-9]+}}, %v24, %v26 3197 ; CHECK: lhi %r2, 0 3198 ; CHECK: lochinhe %r2, 1 3199 ; CHECK: br %r14 3200 %call = call {<2 x i64>, i32} @llvm.s390.vfchdbs(<2 x double> %a, 3201 <2 x double> %b) 3202 %res = extractvalue {<2 x i64>, i32} %call, 1 3203 %cmp = icmp sge i32 %res, 1 3204 %ext = zext i1 %cmp to i32 3205 ret i32 %ext 3206 } 3207 3208 ; VFCHDBS, storing to %ptr if not all elements are higher. 3209 define <2 x i64> @test_vfchdbs_notall_store(<2 x double> %a, <2 x double> %b, 3210 i32 *%ptr) { 3211 ; CHECK-LABEL: test_vfchdbs_notall_store: 3212 ; CHECK-NOT: %r 3213 ; CHECK: vfchdbs %v24, %v24, %v26 3214 ; CHECK-NEXT: {{bher|ber}} %r14 3215 ; CHECK: mvhi 0(%r2), 0 3216 ; CHECK: br %r14 3217 %call = call {<2 x i64>, i32} @llvm.s390.vfchdbs(<2 x double> %a, 3218 <2 x double> %b) 3219 %res = extractvalue {<2 x i64>, i32} %call, 0 3220 %cc = extractvalue {<2 x i64>, i32} %call, 1 3221 %cmp = icmp ugt i32 %cc, 0 3222 br i1 %cmp, label %store, label %exit 3223 3224 store: 3225 store i32 0, i32 *%ptr 3226 br label %exit 3227 3228 exit: 3229 ret <2 x i64> %res 3230 } 3231 3232 ; VFCHEDBS with no processing of the result. 3233 define i32 @test_vfchedbs(<2 x double> %a, <2 x double> %b) { 3234 ; CHECK-LABEL: test_vfchedbs: 3235 ; CHECK: vfchedbs {{%v[0-9]+}}, %v24, %v26 3236 ; CHECK: ipm %r2 3237 ; CHECK: srl %r2, 28 3238 ; CHECK: br %r14 3239 %call = call {<2 x i64>, i32} @llvm.s390.vfchedbs(<2 x double> %a, 3240 <2 x double> %b) 3241 %res = extractvalue {<2 x i64>, i32} %call, 1 3242 ret i32 %res 3243 } 3244 3245 ; VFCHEDBS, returning 1 if neither element is higher or equal. 3246 define i32 @test_vfchedbs_none_bool(<2 x double> %a, <2 x double> %b) { 3247 ; CHECK-LABEL: test_vfchedbs_none_bool: 3248 ; CHECK: vfchedbs {{%v[0-9]+}}, %v24, %v26 3249 ; CHECK: lhi %r2, 0 3250 ; CHECK: lochio %r2, 1 3251 ; CHECK: br %r14 3252 %call = call {<2 x i64>, i32} @llvm.s390.vfchedbs(<2 x double> %a, 3253 <2 x double> %b) 3254 %res = extractvalue {<2 x i64>, i32} %call, 1 3255 %cmp = icmp eq i32 %res, 3 3256 %ext = zext i1 %cmp to i32 3257 ret i32 %ext 3258 } 3259 3260 ; VFCHEDBS, storing to %ptr if neither element is higher or equal. 3261 define <2 x i64> @test_vfchedbs_none_store(<2 x double> %a, <2 x double> %b, 3262 i32 *%ptr) { 3263 ; CHECK-LABEL: test_vfchedbs_none_store: 3264 ; CHECK-NOT: %r 3265 ; CHECK: vfchedbs %v24, %v24, %v26 3266 ; CHECK-NEXT: {{bnor|bler}} %r14 3267 ; CHECK: mvhi 0(%r2), 0 3268 ; CHECK: br %r14 3269 %call = call {<2 x i64>, i32} @llvm.s390.vfchedbs(<2 x double> %a, 3270 <2 x double> %b) 3271 %res = extractvalue {<2 x i64>, i32} %call, 0 3272 %cc = extractvalue {<2 x i64>, i32} %call, 1 3273 %cmp = icmp uge i32 %cc, 3 3274 br i1 %cmp, label %store, label %exit 3275 3276 store: 3277 store i32 0, i32 *%ptr 3278 br label %exit 3279 3280 exit: 3281 ret <2 x i64> %res 3282 } 3283 3284 ; VFTCIDB with the lowest useful class selector and no processing of the result. 3285 define i32 @test_vftcidb(<2 x double> %a) { 3286 ; CHECK-LABEL: test_vftcidb: 3287 ; CHECK: vftcidb {{%v[0-9]+}}, %v24, 1 3288 ; CHECK: ipm %r2 3289 ; CHECK: srl %r2, 28 3290 ; CHECK: br %r14 3291 %call = call {<2 x i64>, i32} @llvm.s390.vftcidb(<2 x double> %a, i32 1) 3292 %res = extractvalue {<2 x i64>, i32} %call, 1 3293 ret i32 %res 3294 } 3295 3296 ; VFTCIDB with the highest useful class selector, returning 1 if all elements 3297 ; have the right class (CC == 0). 3298 define i32 @test_vftcidb_all_bool(<2 x double> %a) { 3299 ; CHECK-LABEL: test_vftcidb_all_bool: 3300 ; CHECK: vftcidb {{%v[0-9]+}}, %v24, 4094 3301 ; CHECK: lhi %r2, 0 3302 ; CHECK: lochie %r2, 1 3303 ; CHECK: br %r14 3304 %call = call {<2 x i64>, i32} @llvm.s390.vftcidb(<2 x double> %a, i32 4094) 3305 %res = extractvalue {<2 x i64>, i32} %call, 1 3306 %cmp = icmp eq i32 %res, 0 3307 %ext = zext i1 %cmp to i32 3308 ret i32 %ext 3309 } 3310 3311 ; VFIDB with a rounding mode not usable via standard intrinsics. 3312 define <2 x double> @test_vfidb_0_4(<2 x double> %a) { 3313 ; CHECK-LABEL: test_vfidb_0_4: 3314 ; CHECK: vfidb %v24, %v24, 0, 4 3315 ; CHECK: br %r14 3316 %res = call <2 x double> @llvm.s390.vfidb(<2 x double> %a, i32 0, i32 4) 3317 ret <2 x double> %res 3318 } 3319 3320 ; VFIDB with IEEE-inexact exception suppressed. 3321 define <2 x double> @test_vfidb_4_0(<2 x double> %a) { 3322 ; CHECK-LABEL: test_vfidb_4_0: 3323 ; CHECK: vfidb %v24, %v24, 4, 0 3324 ; CHECK: br %r14 3325 %res = call <2 x double> @llvm.s390.vfidb(<2 x double> %a, i32 4, i32 0) 3326 ret <2 x double> %res 3327 } 3328 3329
