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53  * Using the pci.c functions of the Etherboot code, the 82557 chip is detected.
61 * The chip is then initialized to "know" its ethernet address, and to
64 * you can write the buffers asynchronously to the chip reading the
76 * We have only one receive buffer. The chip is told to recieve packets,
135 #define EE_CS 0x02 /* EEPROM chip select. */
136 #define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */
137 #define EE_DATA_READ 0x08 /* EEPROM chip data out. */
273 * This probably writes to the "physical media interface chip".
296 * This probably reads a register in the "physical media interface chip".
477 * leaves the ioaddress of the 82557 chip in the variable ioaddr.