Lines Matching refs:eth_nic_base
33 static unsigned short eth_nic_base, eth_asic_base;
112 D8390_COMMAND_STA, eth_nic_base + D8390_P0_COMMAND);
113 outb(cnt, eth_nic_base + D8390_P0_RBCR0);
114 outb(cnt>>8, eth_nic_base + D8390_P0_RBCR1);
115 outb(src, eth_nic_base + D8390_P0_RSAR0);
116 outb(src>>8, eth_nic_base + D8390_P0_RSAR1);
118 D8390_COMMAND_STA, eth_nic_base + D8390_P0_COMMAND);
158 D8390_COMMAND_STA, eth_nic_base + D8390_P0_COMMAND);
159 outb(D8390_ISR_RDC, eth_nic_base + D8390_P0_ISR);
160 outb(cnt, eth_nic_base + D8390_P0_RBCR0);
161 outb(cnt>>8, eth_nic_base + D8390_P0_RBCR1);
162 outb(dst, eth_nic_base + D8390_P0_RSAR0);
163 outb(dst>>8, eth_nic_base + D8390_P0_RSAR1);
165 D8390_COMMAND_STA, eth_nic_base + D8390_P0_COMMAND);
198 (inb(eth_nic_base + D8390_P0_ISR) & D8390_ISR_RDC)
204 while((inb(eth_nic_base + D8390_P0_ISR) & D8390_ISR_RDC)
225 outb(D8390_COMMAND_PS0 | D8390_COMMAND_STP, eth_nic_base+D8390_P0_COMMAND);
229 D8390_COMMAND_STP, eth_nic_base+D8390_P0_COMMAND);
231 outb(0x49, eth_nic_base+D8390_P0_DCR);
233 outb(0x48, eth_nic_base+D8390_P0_DCR);
234 outb(0, eth_nic_base+D8390_P0_RBCR0);
235 outb(0, eth_nic_base+D8390_P0_RBCR1);
236 outb(0x20, eth_nic_base+D8390_P0_RCR); /* monitor mode */
237 outb(2, eth_nic_base+D8390_P0_TCR);
238 outb(eth_tx_start, eth_nic_base+D8390_P0_TPSR);
239 outb(eth_rx_start, eth_nic_base+D8390_P0_PSTART);
241 if (eth_flags & FLAG_790) outb(0, eth_nic_base + 0x09);
243 outb(eth_memsize, eth_nic_base+D8390_P0_PSTOP);
244 outb(eth_memsize - 1, eth_nic_base+D8390_P0_BOUND);
245 outb(0xFF, eth_nic_base+D8390_P0_ISR);
246 outb(0, eth_nic_base+D8390_P0_IMR);
250 D8390_COMMAND_STP, eth_nic_base+D8390_P0_COMMAND);
254 D8390_COMMAND_RD2 | D8390_COMMAND_STP, eth_nic_base+D8390_P0_COMMAND);
256 outb(nic->node_addr[i], eth_nic_base+D8390_P1_PAR0+i);
258 outb(0xFF, eth_nic_base+D8390_P1_MAR0+i);
259 outb(eth_rx_start, eth_nic_base+D8390_P1_CURR);
263 D8390_COMMAND_STA, eth_nic_base+D8390_P0_COMMAND);
267 D8390_COMMAND_RD2 | D8390_COMMAND_STA, eth_nic_base+D8390_P0_COMMAND);
268 outb(0xFF, eth_nic_base+D8390_P0_ISR);
269 outb(0, eth_nic_base+D8390_P0_TCR);
270 outb(4, eth_nic_base+D8390_P0_RCR); /* allow broadcast frames */
296 outb(D8390_COMMAND_PS0 | D8390_COMMAND_STP, eth_nic_base+D8390_P0_COMMAND);
300 D8390_COMMAND_STP, eth_nic_base+D8390_P0_COMMAND);
307 outb(0, eth_nic_base+D8390_P0_RBCR0); /* reset byte counter */
308 outb(0, eth_nic_base+D8390_P0_RBCR1);
316 outb(2, eth_nic_base+D8390_P0_TCR);
319 outb(D8390_COMMAND_PS0 | D8390_COMMAND_STA, eth_nic_base+D8390_P0_COMMAND);
323 D8390_COMMAND_STA, eth_nic_base+D8390_P0_COMMAND);
330 outb(D8390_ISR_OVW, eth_nic_base+D8390_P0_ISR);
333 outb(0, eth_nic_base+D8390_P0_TCR);
409 D8390_COMMAND_STA, eth_nic_base+D8390_P0_COMMAND);
413 D8390_COMMAND_RD2 | D8390_COMMAND_STA, eth_nic_base+D8390_P0_COMMAND);
414 outb(eth_tx_start, eth_nic_base+D8390_P0_TPSR);
415 outb(s, eth_nic_base+D8390_P0_TBCR0);
416 outb(s>>8, eth_nic_base+D8390_P0_TBCR1);
420 D8390_COMMAND_TXP | D8390_COMMAND_STA, eth_nic_base+D8390_P0_COMMAND);
425 D8390_COMMAND_STA, eth_nic_base+D8390_P0_COMMAND);
442 if (!eth_drain_receiver && (inb(eth_nic_base+D8390_P0_ISR) & D8390_ISR_OVW)) {
447 rstat = inb(eth_nic_base+D8390_P0_RSR);
449 next = inb(eth_nic_base+D8390_P0_BOUND)+1;
451 outb(D8390_COMMAND_PS1, eth_nic_base+D8390_P0_COMMAND);
452 curr = inb(eth_nic_base+D8390_P1_CURR);
453 outb(D8390_COMMAND_PS0, eth_nic_base+D8390_P0_COMMAND);
515 eth_nic_base+D8390_P0_BOUND);
562 eth_nic_base = eth_asic_base + WD_NIC_ADDR;
641 for (idx = 0; (eth_nic_base = base[idx]) != 0; ++idx) {
643 eth_asic_base = eth_nic_base + _3COM_ASIC_OFFSET;
711 printf("\n3Com 3c503 base %#hx, ", eth_nic_base);
717 nic->node_addr[i] = inb(eth_nic_base+i);
768 for (idx = 0; (eth_nic_base = probe_addrs[idx]) != 0; ++idx) {
770 eth_asic_base = eth_nic_base + NE_ASIC_OFFSET;
778 D8390_COMMAND_RD2, eth_nic_base + D8390_P0_COMMAND);
779 outb(D8390_RCR_MON, eth_nic_base + D8390_P0_RCR);
780 outb(D8390_DCR_FT1 | D8390_DCR_LS, eth_nic_base + D8390_P0_DCR);
781 outb(MEM_8192, eth_nic_base + D8390_P0_PSTART);
782 outb(MEM_16384, eth_nic_base + D8390_P0_PSTOP);
796 D8390_DCR_FT1 | D8390_DCR_LS, eth_nic_base + D8390_P0_DCR);
797 outb(MEM_16384, eth_nic_base + D8390_P0_PSTART);
798 outb(MEM_32768, eth_nic_base + D8390_P0_PSTOP);
804 if (eth_nic_base == 0)
806 if (eth_nic_base > ISA_MAX_ADDR) /* PCI probably */
814 (eth_flags & FLAG_16BIT) ? '2' : '1', eth_nic_base,
