Lines Matching full:clock
339 #define EE_SHIFT_CLK 0x02 /* EEPROM shift clock. */
347 /* Delay between EEPROM clock transitions. Even at 33Mhz current PCI
348 implementations don't overrun the EEPROM clock. We add a bus
552 /* The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
559 to not share code. The maxium data clock rate is 2.5 Mhz. */
