Lines Matching refs:tlb
16 #define tlb_flush(tlb) ((void) tlb)
46 * MMU TLB Model
52 * v4wb - ARMv4 with write buffer without I TLB flush entry instruction
53 * v4wbi - ARMv4 with write buffer with I TLB flush entry instruction
54 * v6wbi - ARMv6 with write buffer with I TLB flush entry instruction
142 #error Unknown TLB model
176 * TLB Management
179 * The arch/arm/mm/tlb-*.S files implement these methods.
181 * The TLB specific code is expected to perform whatever tests it
182 * needs to determine if it should invalidate the TLB for each
188 * Invalidate the entire TLB.
192 * Invalidate all TLB entries in a particular address
198 * Invalidate a range of TLB entries in the specified
212 * Invalidate the TLB entry for the specified page. The address
214 * only require the D-TLB to be invalidated.
220 * - building a set of TLB flags that might be set in __cpu_tlb_flags
221 * - building a set of TLB flags that will always be set in __cpu_tlb_flags
350 /* The ARM ARM states that the completion of a TLB maintenance
361 * RAM if the TLB for the CPU we are running on requires this.
426 * ARM processors do not cache TLB tables in RAM.
