Lines Matching full:power
192 #define PCI_CAP_ID_PM 0x01 /* Power Management */
208 /* Power Management Registers */
215 #define PCI_PM_CAP_AUX_POWER 0x01C0 /* Auxilliary power support mask */
216 #define PCI_PM_CAP_D1 0x0200 /* D1 power state support */
217 #define PCI_PM_CAP_D2 0x0400 /* D2 power state support */
226 #define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
234 #define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */
345 #define PCI_EXP_DEVCAP_PWR_IND 0x4000 /* Power Indicator Present */
346 #define PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value */
347 #define PCI_EXP_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale */
357 #define PCI_EXP_DEVCTL_AUX_PME 0x0400 /* Auxiliary Power PM Enable */
365 #define PCI_EXP_DEVSTA_AUXPD 0x10 /* AUX Power Detected */
454 /* Power Budgeting */
457 #define PCI_PWR_DATA_BASE(x) ((x) & 0xff) /* Base Power */
462 #define PCI_PWR_DATA_RAIL(x) (((x) >> 18) & 7) /* Power Rail */
