Lines Matching full:mask
35 #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
68 #define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */
69 #define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */
70 #define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */
71 #define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */
72 #define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */
74 #define UART_FCR6_R_TRIGGER_8 0x00 /* Mask for receive trigger set at 1 */
75 #define UART_FCR6_R_TRIGGER_16 0x40 /* Mask for receive trigger set at 4 */
76 #define UART_FCR6_R_TRIGGER_24 0x80 /* Mask for receive trigger set at 8 */
77 #define UART_FCR6_R_TRIGGER_28 0xC0 /* Mask for receive trigger set at 14 */
78 #define UART_FCR6_T_TRIGGER_16 0x00 /* Mask for transmit trigger set at 16 */
79 #define UART_FCR6_T_TRIGGER_8 0x10 /* Mask for transmit trigger set at 8 */
80 #define UART_FCR6_T_TRIGGER_24 0x20 /* Mask for transmit trigger set at 24 */
81 #define UART_FCR6_T_TRIGGER_30 0x30 /* Mask for transmit trigger set at 30 */
