Lines Matching full:cache
106 "data cache access, cacheable locations"},
108 "data cache access, all locations"},
110 "data cache miss"},
112 "data cache writeback, 1 event for every half cacheline"},
130 "Instruction fetch misses from cache or normal cacheable memory"},
134 "Data R/W operation that causes a refill from cache or normal cacheable"
137 "Data R/W from cache"},
170 "Any store that is merged in L2 cache"},
172 "Any bufferable store from load/store to L2 cache"},
174 "Any access to L2 cache"},
176 "Any cacheable miss in L2 cache"},
186 "L1 data cache miss as a result of the hashing algorithm"},
188 "L1 instruction cache miss as a result of the hashing algorithm"},
192 "NEON data access that hits L1 cache"},
194 "NEON cacheable data access that hits L1 cache"},
198 "Any NEON hit in L2 cache"},
200 "Any L1 instruction cache access, excluding CP15 cache accesses"},
