Lines Matching full:addr
166 int addr_diff = ptr->addr - prev_addr;
168 prev_addr = ptr->addr;
181 void dcache_load(uint32_t addr)
185 uint32_t cache_addr = addr >> dcache.log_line_size;
187 //printf("ld %lld 0x%x\n", sim_time, addr);
192 printf("dcache load hit addr: 0x%x cache_addr: 0x%x row %d way %d\n",
193 addr, cache_addr, row, ii);
198 next->addr = addr;
215 fprintf(ftrace_debug, "t%lld %08x\n", sim_time, addr);
219 next->addr = addr;
259 printf("dcache load miss addr: 0x%x cache_addr: 0x%x row %d replacing way %d\n",
260 addr, cache_addr, row, way);
267 void dcache_store(uint32_t addr, uint32_t val)
269 //printf("st %lld 0x%08x val 0x%x\n", sim_time, addr, val);
273 uint32_t cache_addr = addr >> dcache.log_line_size;
279 printf("dcache store hit addr: 0x%x cache_addr: 0x%x row %d way %d\n",
280 addr, cache_addr, row, ii);
285 next->addr = addr;
300 printf("dcache store miss addr: 0x%x cache_addr: 0x%x row %d\n",
301 addr, cache_addr, row);
306 fprintf(ftrace_debug, "t%lld %08x\n", sim_time, addr);
311 next->addr = addr;
330 void dcache_swp(uint32_t addr)
332 dcache_load(addr);
333 dcache_store(addr, 0);
