Lines Matching full:addr
207 #define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK)
217 static void map_exec(void *addr, long size)
220 VirtualProtect(addr, size,
225 static void map_exec(void *addr, long size)
230 start = (unsigned long)addr;
233 end = (unsigned long)addr + size;
324 unsigned long addr = h2g(p);
325 page_set_flags(addr & TARGET_PAGE_MASK,
326 TARGET_PAGE_ALIGN(addr + len),
470 void *addr = NULL;
476 addr = (void *)0x40000000;
481 code_gen_buffer = mmap(addr, code_gen_buffer_size,
1083 static void tb_invalidate_phys_page(target_phys_addr_t addr,
1098 addr &= TARGET_PAGE_MASK;
1099 p = page_find(addr >> TARGET_PAGE_BITS);
1126 tb_phys_invalidate(tb, addr);
1161 target_ulong addr;
1169 for(addr = page_addr; addr < page_addr + qemu_host_page_size;
1170 addr += TARGET_PAGE_SIZE) {
1172 p2 = page_find (addr >> TARGET_PAGE_BITS);
1177 page_get_flags(addr);
1349 target_phys_addr_t addr;
1354 addr = cpu_get_phys_page_debug(env, pc);
1355 p = phys_page_find(addr >> TARGET_PAGE_BITS);
1367 int cpu_watchpoint_insert(CPUState *env, target_ulong addr, target_ulong len,
1374 if ((len != 1 && len != 2 && len != 4 && len != 8) || (addr & ~len_mask)) {
1376 TARGET_FMT_lx ", len=" TARGET_FMT_lu "\n", addr, len);
1381 wp->vaddr = addr;
1391 tlb_flush_page(env, addr);
1399 int cpu_watchpoint_remove(CPUState *env, target_ulong addr, target_ulong len,
1406 if (addr == wp->vaddr && len_mask == wp->len_mask
1767 static inline void tlb_flush_jmp_cache(CPUState *env, target_ulong addr)
1773 i = tb_jmp_cache_hash_page(addr - TARGET_PAGE_SIZE);
1777 i = tb_jmp_cache_hash_page(addr);
1814 static inline void tlb_flush_entry(CPUTLBEntry *tlb_entry, target_ulong addr)
1816 if (addr == (tlb_entry->addr_read &
1818 addr == (tlb_entry->addr_write &
1820 addr == (tlb_entry->addr_code &
1828 void tlb_flush_page(CPUState *env, target_ulong addr)
1834 printf("tlb_flush_page: " TARGET_FMT_lx "\n", addr);
1840 addr &= TARGET_PAGE_MASK;
1841 i = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
1843 tlb_flush_entry(&env->tlb_table[mmu_idx][i], addr);
1845 tlb_flush_jmp_cache(env, addr);
1849 kqemu_flush_page(env, addr);
1854 /* update the TLBs so that writes to code in the virtual page 'addr'
1874 unsigned long addr;
1876 addr = (tlb_entry->addr_write & TARGET_PAGE_MASK) + tlb_entry->addend;
1877 if ((addr - start) < length) {
1903 ram_addr_t addr;
1904 addr = start;
1906 kqemu_set_notdirty(env, addr);
1907 addr += TARGET_PAGE_SIZE;
2145 void tlb_flush_page(CPUState *env, target_ulong addr)
2238 target_ulong addr;
2245 for(addr = start; addr < end; addr += TARGET_PAGE_SIZE) {
2246 p = page_find_alloc(addr >> TARGET_PAGE_BITS);
2256 tb_invalidate_phys_page(addr, 0, NULL);
2266 target_ulong addr;
2275 for(addr = start; addr < end; addr += TARGET_PAGE_SIZE) {
2276 p = page_find(addr >> TARGET_PAGE_BITS);
2290 if (!page_unprotect(addr, 0, NULL))
2305 target_ulong host_start, host_end, addr;
2322 for(addr = host_start;addr < host_end; addr += TARGET_PAGE_SIZE) {
2349 unsigned long addr, target_ulong vaddr)
2360 #define CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2, \
2363 if (addr > start_addr) \
2371 if ((start_addr + orig_size) - addr >= TARGET_PAGE_SIZE) \
2392 target_phys_addr_t addr, end_addr;
2414 for(addr = start_addr; addr != end_addr; addr += TARGET_PAGE_SIZE) {
2415 p = phys_page_find(addr >> TARGET_PAGE_BITS);
2421 CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2,
2425 subpage = subpage_init((addr & TARGET_PAGE_MASK),
2442 p = phys_page_find_alloc(addr >> TARGET_PAGE_BITS, 1);
2452 CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr,
2456 subpage = subpage_init((addr & TARGET_PAGE_MASK),
2458 addr & TARGET_PAGE_MASK);
2477 ram_addr_t cpu_get_physical_page_desc(target_phys_addr_t addr)
2481 p = phys_page_find(addr >> TARGET_PAGE_BITS);
2487 void qemu_register_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size)
2490 kvm_coalesce_mmio_region(addr, size);
2493 void qemu_unregister_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size)
2496 kvm_uncoalesce_mmio_region(addr, size);
2503 ram_addr_t addr;
2509 addr = last_ram_offset;
2511 return addr;
2548 void qemu_ram_free(ram_addr_t addr)
2561 void *qemu_get_ram_ptr(ram_addr_t addr)
2569 return kqemu_phys_ram_base + addr;
2576 while (block && (block->offset > addr
2577 || block->offset + block->length <= addr)) {
2584 fprintf(stderr, "Bad ram offset %" PRIx64 "\n", (uint64_t)addr);
2593 return block->host + (addr - block->offset);
2628 static uint32_t unassigned_mem_readb(void *opaque, target_phys_addr_t addr)
2631 printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
2634 do_unassigned_access(addr, 0, 0, 0, 1);
2639 static uint32_t unassigned_mem_readw(void *opaque, target_phys_addr_t addr)
2642 printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
2645 do_unassigned_access(addr, 0, 0, 0, 2);
2650 static uint32_t unassigned_mem_readl(void *opaque, target_phys_addr_t addr)
2653 printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
2656 do_unassigned_access(addr, 0, 0, 0, 4);
2661 static void unassigned_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
2664 printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val);
2667 do_unassigned_access(addr, 1, 0, 0, 1);
2671 static void unassigned_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
2674 printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val);
2677 do_unassigned_access(addr, 1, 0, 0, 2);
2681 static void unassigned_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
2684 printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val);
2687 do_unassigned_access(addr, 1, 0, 0, 4);
2838 static uint32_t watch_mem_readb(void *opaque, target_phys_addr_t addr)
2840 check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x0, BP_MEM_READ);
2841 return ldub_phys(addr);
2844 static uint32_t watch_mem_readw(void *opaque, target_phys_addr_t addr)
2846 check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x1, BP_MEM_READ);
2847 return lduw_phys(addr);
2850 static uint32_t watch_mem_readl(void *opaque, target_phys_addr_t addr)
2852 check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x3, BP_MEM_READ);
2853 return ldl_phys(addr);
2856 static void watch_mem_writeb(void *opaque, target_phys_addr_t addr,
2859 check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x0, BP_MEM_WRITE);
2860 stb_phys(addr, val);
2863 static void watch_mem_writew(void *opaque, target_phys_addr_t addr,
2866 check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x1, BP_MEM_WRITE);
2867 stw_phys(addr, val);
2870 static void watch_mem_writel(void *opaque, target_phys_addr_t addr,
2873 check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x3, BP_MEM_WRITE);
2874 stl_phys(addr, val);
2889 static inline uint32_t subpage_readlen (subpage_t *mmio, target_phys_addr_t addr,
2895 idx = SUBPAGE_IDX(addr);
2897 printf("%s: subpage %p len %d addr " TARGET_FMT_plx " idx %d\n", __func__,
2898 mmio, len, addr, idx);
2901 addr + mmio->region_offset[idx][0][len]);
2906 static inline void subpage_writelen (subpage_t *mmio, target_phys_addr_t addr,
2911 idx = SUBPAGE_IDX(addr);
2913 printf("%s: subpage %p len %d addr " TARGET_FMT_plx " idx %d value %08x\n", __func__,
2914 mmio, len, addr, idx, value);
2917 addr + mmio->region_offset[idx][1][len],
2921 static uint32_t subpage_readb (void *opaque, target_phys_addr_t addr)
2924 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
2927 return subpage_readlen(opaque, addr, 0);
2930 static void subpage_writeb (void *opaque, target_phys_addr_t addr,
2934 printf("%s: addr " TARGET_FMT_plx " val %08x\n", __func__, addr, value);
2936 subpage_writelen(opaque, addr, value, 0);
2939 static uint32_t subpage_readw (void *opaque, target_phys_addr_t addr)
2942 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
2945 return subpage_readlen(opaque, addr, 1);
2948 static void subpage_writew (void *opaque, target_phys_addr_t addr,
2952 printf("%s: addr " TARGET_FMT_plx " val %08x\n", __func__, addr, value);
2954 subpage_writelen(opaque, addr, value, 1);
2957 static uint32_t subpage_readl (void *opaque, target_phys_addr_t addr)
2960 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
2963 return subpage_readlen(opaque, addr, 2);
2967 target_phys_addr_t addr, uint32_t value)
2970 printf("%s: addr " TARGET_FMT_plx " val %08x\n", __func__, addr, value);
2972 subpage_writelen(opaque, addr, value, 2);
3133 void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
3141 page = addr & TARGET_PAGE_MASK;
3142 l = (page + TARGET_PAGE_SIZE) - addr;
3152 if (!(p = lock_user(VERIFY_WRITE, addr, l, 0)))
3156 unlock_user(p, addr, l);
3161 if (!(p = lock_user(VERIFY_READ, addr, l, 1)))
3165 unlock_user(p, addr, 0);
3169 addr += l;
3174 void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
3185 page = addr & TARGET_PAGE_MASK;
3186 l = (page + TARGET_PAGE_SIZE) - addr;
3198 target_phys_addr_t addr1 = addr;
3201 addr1 = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
3222 addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
3237 addr;
3241 addr1 = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
3261 (addr & ~TARGET_PAGE_MASK);
3267 addr += l;
3272 void cpu_physical_memory_write_rom(target_phys_addr_t addr,
3282 page = addr & TARGET_PAGE_MASK;
3283 l = (page + TARGET_PAGE_SIZE) - addr;
3299 addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
3306 addr += l;
3312 target_phys_addr_t addr;
3362 void *cpu_physical_memory_map(target_phys_addr_t addr,
3377 page = addr & TARGET_PAGE_MASK;
3378 l = (page + TARGET_PAGE_SIZE) - addr;
3393 bounce.addr = addr;
3396 cpu_physical_memory_rw(addr, bounce.buffer, l, 0);
3400 addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
3410 addr += l;
3446 cpu_physical_memory_write(bounce.addr, bounce.buffer, access_len);
3453 /* warning: addr must be aligned */
3454 uint32_t ldl_phys(target_phys_addr_t addr)
3462 p = phys_page_find(addr >> TARGET_PAGE_BITS);
3474 addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
3475 val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr);
3479 (addr & ~TARGET_PAGE_MASK);
3485 /* warning: addr must be aligned */
3486 uint64_t ldq_phys(target_phys_addr_t addr)
3494 p = phys_page_find(addr >> TARGET_PAGE_BITS);
3506 addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
3508 val = (uint64_t)io_mem_read[io_index][2](io_mem_opaque[io_index], addr) << 32;
3509 val |= io_mem_read[io_index][2](io_mem_opaque[io_index], addr + 4);
3511 val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr);
3512 val |= (uint64_t)io_mem_read[io_index][2](io_mem_opaque[io_index], addr + 4) << 32;
3517 (addr & ~TARGET_PAGE_MASK);
3524 uint32_t ldub_phys(target_phys_addr_t addr)
3527 cpu_physical_memory_read(addr, &val, 1);
3532 uint32_t lduw_phys(target_phys_addr_t addr)
3535 cpu_physical_memory_read(addr, (uint8_t *)&val, 2);
3539 /* warning: addr must be aligned. The ram page is not masked as dirty
3542 void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val)
3549 p = phys_page_find(addr >> TARGET_PAGE_BITS);
3559 addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
3560 io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val);
3562 unsigned long addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
3578 void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val)
3585 p = phys_page_find(addr >> TARGET_PAGE_BITS);
3595 addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
3597 io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val >> 32);
3598 io_mem_write[io_index][2](io_mem_opaque[io_index], addr + 4, val);
3600 io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val);
3601 io_mem_write[io_index][2](io_mem_opaque[io_index], addr + 4, val >> 32);
3605 (addr & ~TARGET_PAGE_MASK);
3610 /* warning: addr must be aligned */
3611 void stl_phys(target_phys_addr_t addr, uint32_t val)
3618 p = phys_page_find(addr >> TARGET_PAGE_BITS);
3628 addr = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
3629 io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val);
3632 addr1 = (pd & TARGET_PAGE_MASK) + (addr & ~TARGET_PAGE_MASK);
3647 void stb_phys(target_phys_addr_t addr, uint32_t val)
3650 cpu_physical_memory_write(addr, &v, 1);
3654 void stw_phys(target_phys_addr_t addr, uint32_t val)
3657 cpu_physical_memory_write(addr, (const uint8_t *)&v, 2);
3661 void stq_phys(target_phys_addr_t addr, uint64_t val)
3664 cpu_physical_memory_write(addr, (const uint8_t *)&val, 8);
3670 int cpu_memory_rw_debug(CPUState *env, target_ulong addr,
3678 page = addr & TARGET_PAGE_MASK;
3683 l = (page + TARGET_PAGE_SIZE) - addr;
3686 phys_addr += (addr & ~TARGET_PAGE_MASK);
3695 addr += l;
