Lines Matching defs:irq_state
52 #define GIC_SET_ENABLED(irq) s->irq_state[irq].enabled = 1
53 #define GIC_CLEAR_ENABLED(irq) s->irq_state[irq].enabled = 0
54 #define GIC_TEST_ENABLED(irq) s->irq_state[irq].enabled
55 #define GIC_SET_PENDING(irq, cm) s->irq_state[irq].pending |= (cm)
56 #define GIC_CLEAR_PENDING(irq, cm) s->irq_state[irq].pending &= ~(cm)
57 #define GIC_TEST_PENDING(irq, cm) ((s->irq_state[irq].pending & (cm)) != 0)
58 #define GIC_SET_ACTIVE(irq, cm) s->irq_state[irq].active |= (cm)
59 #define GIC_CLEAR_ACTIVE(irq, cm) s->irq_state[irq].active &= ~(cm)
60 #define GIC_TEST_ACTIVE(irq, cm) ((s->irq_state[irq].active & (cm)) != 0)
61 #define GIC_SET_MODEL(irq) s->irq_state[irq].model = 1
62 #define GIC_CLEAR_MODEL(irq) s->irq_state[irq].model = 0
63 #define GIC_TEST_MODEL(irq) s->irq_state[irq].model
64 #define GIC_SET_LEVEL(irq, cm) s->irq_state[irq].level = (cm)
65 #define GIC_CLEAR_LEVEL(irq, cm) s->irq_state[irq].level &= ~(cm)
66 #define GIC_TEST_LEVEL(irq, cm) ((s->irq_state[irq].level & (cm)) != 0)
67 #define GIC_SET_TRIGGER(irq) s->irq_state[irq].trigger = 1
68 #define GIC_CLEAR_TRIGGER(irq) s->irq_state[irq].trigger = 0
69 #define GIC_TEST_TRIGGER(irq) s->irq_state[irq].trigger
85 gic_irq_state irq_state[GIC_NIRQ];
622 memset(s->irq_state, 0, GIC_NIRQ * sizeof(gic_irq_state));
672 qemu_put_byte(f, s->irq_state[i].enabled);
673 qemu_put_byte(f, s->irq_state[i].pending);
674 qemu_put_byte(f, s->irq_state[i].active);
675 qemu_put_byte(f, s->irq_state[i].level);
676 qemu_put_byte(f, s->irq_state[i].model);
677 qemu_put_byte(f, s->irq_state[i].trigger);
709 s->irq_state[i].enabled = qemu_get_byte(f);
710 s->irq_state[i].pending = qemu_get_byte(f);
711 s->irq_state[i].active = qemu_get_byte(f);
712 s->irq_state[i].level = qemu_get_byte(f);
713 s->irq_state[i].model = qemu_get_byte(f);
714 s->irq_state[i].trigger = qemu_get_byte(f);
