Lines Matching full:cell
166 /* Opcode is only supported by PowerPC Cell family. */
1963 #define CELL PPC_OPCODE_CELL
3156 { "hrfid", XL(19,274), 0xffffffff, POWER5 | CELL, { 0 } },
4109 { "cctpl", 0x7c210b78, 0xffffffff, CELL, { 0 }},
4110 { "cctpm", 0x7c421378, 0xffffffff, CELL, { 0 }},
4111 { "cctph", 0x7c631b78, 0xffffffff, CELL, { 0 }},
4112 { "db8cyc", 0x7f9ce378, 0xffffffff, CELL, { 0 }},
4113 { "db10cyc", 0x7fbdeb78, 0xffffffff, CELL, { 0 }},
4114 { "db12cyc", 0x7fdef378, 0xffffffff, CELL, { 0 }},
4115 { "db16cyc", 0x7ffffb78, 0xffffffff, CELL, { 0 }},
4375 { "ldbrx", X(31,532), X_MASK, CELL, { RT, RA0, RB } },
4438 { "stdbrx", X(31,660), X_MASK, CELL, { RS, RA0, RB } },
4618 /* New load/store left/right index vector instructions that are in the Cell only. */
4619 { "lvlx", X(31, 519), X_MASK, CELL, { VD, RA0, RB } },
4620 { "lvlxl", X(31, 775), X_MASK, CELL, { VD, RA0, RB } },
4621 { "lvrx", X(31, 551), X_MASK, CELL, { VD, RA0, RB } },
4622 { "lvrxl", X(31, 807), X_MASK, CELL, { VD, RA0, RB } },
4623 { "stvlx", X(31, 647), X_MASK, CELL, { VS, RA0, RB } },
4624 { "stvlxl", X(31, 903), X_MASK, CELL, { VS, RA0, RB } },
4625 { "stvrx", X(31, 679), X_MASK, CELL, { VS, RA0, RB } },
4626 { "stvrxl", X(31, 935), X_MASK, CELL, { VS, RA0, RB } },
5140 && strstr (info->disassembler_options, "cell") != NULL)
