Lines Matching full:mask
56 /* The opcode mask. This is used by the disassembler. This is a
57 mask containing ones indicating those bits which must match the
60 unsigned long mask;
1174 /* FXM mask in mfcr and mtcrf instructions. */
1183 one bit of the mask field is set. */
1188 *errmsg = _("invalid mask field");
1214 *errmsg = _("ignoring invalid mfcr mask");
1226 long mask = (insn >> 12) & 0xff;
1231 /* Exactly one bit of MASK should be set. */
1232 if (mask == 0 || (mask & -mask) != mask)
1236 /* Check that non-power4 form of mfcr has a zero MASK. */
1239 if (mask != 0)
1243 return mask;
1257 unsigned long uval, mask;
1280 for (mx = 0, mask = 1L << 31; mx < 32; ++mx, mask >>= 1)
1282 if ((uval & mask) && !last)
1288 else if (!(uval & mask) && last)
1668 /* The main opcode mask with the RA field clear. */
1720 /* The mask for an VX form instruction. */
1726 /* The mask for an VA form instruction. */
1732 /* The mask for a VXR form instruction. */
1747 /* The mask for an X form instruction. */
1750 /* The mask for a Z form instruction. */
1766 /* An XRT_MASK mask with the L bits clear. */
1784 /* The mask for an X form comparison instruction. */
1787 /* The mask for an X form comparison instruction with the L field
1826 /* The mask for an XL form instruction. */
1850 /* A mask for branch instructions using the BH field. */
1871 /* A mask for the FXM version of an XFX form instruction. */
2000 NAME OPCODE MASK FLAGS { OPERANDS }
2004 MASK is the opcode mask; this is used to tell the disassembler
5034 rotate-left-and-mask, because the underlying instructions support
5300 if ((insn & opcode->mask) != opcode->opcode
