Lines Matching full:case
546 case 0: /* LSL */
553 case 1: /* LSR */
566 case 2: /* ASR */
575 case 3: /* ROR/RRX */
597 case 0: gen_helper_shl_cc(var, var, shift); break;
598 case 1: gen_helper_shr_cc(var, var, shift); break;
599 case 2: gen_helper_sar_cc(var, var, shift); break;
600 case 3: gen_helper_ror_cc(var, var, shift); break;
604 case 0: gen_helper_shl(var, var, shift); break;
605 case 1: gen_helper_shr(var, var, shift); break;
606 case 2: gen_helper_sar(var, var, shift); break;
607 case 3: gen_helper_ror(var, var, shift); break;
615 case 0: gen_pas_helper(glue(pfx,add16)); break; \
616 case 1: gen_pas_helper(glue(pfx,addsubx)); break; \
617 case 2: gen_pas_helper(glue(pfx,subaddx)); break; \
618 case 3: gen_pas_helper(glue(pfx,sub16)); break; \
619 case 4: gen_pas_helper(glue(pfx,add8)); break; \
620 case 7: gen_pas_helper(glue(pfx,sub8)); break; \
628 case 1:
633 case 5:
640 case 2:
643 case 3:
646 case 6:
649 case 7:
660 case 0: gen_pas_helper(glue(pfx,add8)); break; \
661 case 1: gen_pas_helper(glue(pfx,add16)); break; \
662 case 2: gen_pas_helper(glue(pfx,addsubx)); break; \
663 case 4: gen_pas_helper(glue(pfx,sub8)); break; \
664 case 5: gen_pas_helper(glue(pfx,sub16)); break; \
665 case 6: gen_pas_helper(glue(pfx,subaddx)); break; \
673 case 0:
678 case 4:
685 case 1:
688 case 2:
691 case 5:
694 case 6:
709 case 0: /* eq: Z */
713 case 1: /* ne: !Z */
717 case 2: /* cs: C */
721 case 3: /* cc: !C */
725 case 4: /* mi: N */
729 case 5: /* pl: !N */
733 case 6: /* vs: V */
737 case 7: /* vc: !V */
741 case 8: /* hi: C && !Z */
750 case 9: /* ls: !C || Z */
757 case 10: /* ge: N == V -> N ^ V == 0 */
764 case 11: /* lt: N != V -> N ^ V != 0 */
771 case 12: /* gt: !Z && N == V */
783 case 13: /* le: Z || N != V */
1628 case 0x000: /* WOR */
1639 case 0x011: /* TMCR */
1645 case ARM_IWMMXT_wCID:
1646 case ARM_IWMMXT_wCASF:
1648 case ARM_IWMMXT_wCon:
1651 case ARM_IWMMXT_wCSSF:
1657 case ARM_IWMMXT_wCGR0:
1658 case ARM_IWMMXT_wCGR1:
1659 case ARM_IWMMXT_wCGR2:
1660 case ARM_IWMMXT_wCGR3:
1669 case 0x100: /* WXOR */
1680 case 0x111: /* TMRC */
1688 case 0x300: /* WANDN */
1700 case 0x200: /* WAND */
1711 case 0x810: case 0xa10: /* WMADD */
1723 case 0x10e: case 0x50e: case 0x90e: case 0xd0e: /* WUNPCKIL */
1729 case 0:
1732 case 1:
1735 case 2:
1738 case 3:
1745 case 0x10c: case 0x50c: case 0x90c: case 0xd0c: /* WUNPCKIH */
1751 case 0:
1754 case 1:
1757 case 2:
1760 case 3:
1767 case 0x012: case 0x112: case 0x412: case 0x512: /* WSAD */
1781 case 0x010: case 0x110: case 0x210: case 0x310: /* WMUL */
1800 case 0x410: case 0x510: case 0x610: case 0x710: /* WMAC */
1816 case 0x006: case 0x406: case 0x806: case 0xc06: /* WCMPEQ */
1822 case 0:
1825 case 1:
1828 case 2:
1831 case 3:
1838 case 0x800: case 0x900: case 0xc00: case 0xd00: /* WAVG2 */
1858 case 0x802: case 0x902: case 0xa02: case 0xb02: /* WALIGNR */
1870 case 0x601: case 0x605: case 0x609: case 0x60d: /* TINSR */
1876 case 0:
1880 case 1:
1884 case 2:
1888 case 3:
1894 case 0x107: case 0x507: case 0x907: case 0xd07: /* TEXTRM */
1901 case 0:
1908 case 1:
1915 case 2:
1918 case 3:
1923 case 0x117: case 0x517: case 0x917: case 0xd17: /* TEXTRC */
1928 case 0:
1931 case 1:
1934 case 2:
1937 case 3:
1943 case 0x401: case 0x405: case 0x409: case 0x40d: /* TBCST */
1948 case 0:
1951 case 1:
1954 case 2:
1957 case 3:
1963 case 0x113: case 0x513: case 0x913: case 0xd13: /* TANDC */
1968 case 0:
1974 case 1:
1980 case 2:
1984 case 3:
1989 case 0x01c: case 0x41c: case 0x81c: case 0xc1c: /* WACC */
1994 case 0:
1997 case 1:
2000 case 2:
2003 case 3:
2009 case 0x115: case 0x515: case 0x915: case 0xd15: /* TORC */
2014 case 0:
2020 case 1:
2026 case 2:
2030 case 3:
2035 case 0x103: case 0x503: case 0x903: case 0xd03: /* TMOVMSK */
2042 case 0:
2045 case 1:
2048 case 2:
2051 case 3:
2056 case 0x106: case 0x306: case 0x506: case 0x706: /* WCMPGT */
2057 case 0x906: case 0xb06: case 0xd06: case 0xf06:
2063 case 0:
2069 case 1:
2075 case 2:
2081 case 3:
2088 case 0x00e: case 0x20e: case 0x40e: case 0x60e: /* WUNPCKEL */
2089 case 0x80e: case 0xa0e: case 0xc0e: case 0xe0e:
2094 case 0:
2100 case 1:
2106 case 2:
2112 case 3:
2119 case 0x00c: case 0x20c: case 0x40c: case 0x60c: /* WUNPCKEH */
2120 case 0x80c: case 0xa0c: case 0xc0c: case 0xe0c:
2125 case 0:
2131 case 1:
2137 case 2:
2143 case 3:
2150 case 0x204: case 0x604: case 0xa04: case 0xe04: /* WSRL */
2151 case 0x214: case 0x614: case 0xa14: case 0xe14:
2158 case 0:
2160 case 1:
2163 case 2:
2166 case 3:
2174 case 0x004: case 0x404: case 0x804: case 0xc04: /* WSRA */
2175 case 0x014: case 0x414: case 0x814: case 0xc14:
2182 case 0:
2184 case 1:
2187 case 2:
2190 case 3:
2198 case 0x104: case 0x504: case 0x904: case 0xd04: /* WSLL */
2199 case 0x114: case 0x514: case 0x914: case 0xd14:
2206 case 0:
2208 case 1:
2211 case 2:
2214 case 3:
2222 case 0x304: case 0x704: case 0xb04: case 0xf04: /* WROR */
2223 case 0x314: case 0x714: case 0xb14: case 0xf14:
2228 case 0:
2230 case 1:
2235 case 2:
2240 case 3:
2250 case 0x116: case 0x316: case 0x516: case 0x716: /* WMIN */
2251 case 0x916: case 0xb16: case 0xd16: case 0xf16:
2257 case 0:
2263 case 1:
2269 case 2:
2275 case 3:
2281 case 0x016: case 0x216: case 0x416: case 0x616: /* WMAX */
2282 case 0x816: case 0xa16: case 0xc16: case 0xe16:
2288 case 0:
2294 case 1:
2300 case 2:
2306 case 3:
2312 case 0x002: case 0x102: case 0x202: case 0x302: /* WALIGNI */
2313 case 0x402: case 0x502: case 0x602: case 0x702:
2323 case 0x01a: case 0x11a: case 0x21a: case 0x31a: /* WSUB */
2324 case 0x41a: case 0x51a: case 0x61a: case 0x71a:
2325 case 0x81a: case 0x91a: case 0xa1a: case 0xb1a:
2326 case 0xc1a: case 0xd1a: case 0xe1a: case 0xf1a:
2332 case 0x0:
2335 case 0x1:
2338 case 0x3:
2341 case 0x4:
2344 case 0x5:
2347 case 0x7:
2350 case 0x8:
2353 case 0x9:
2356 case 0xb:
2366 case 0x01e: case 0x11e: case 0x21e: case 0x31e: /* WSHUFH */
2367 case 0x41e: case 0x51e: case 0x61e: case 0x71e:
2368 case 0x81e: case 0x91e: case 0xa1e: case 0xb1e:
2369 case 0xc1e: case 0xd1e: case 0xe1e: case 0xf1e:
2379 case 0x018: case 0x118: case 0x218: case 0x318: /* WADD */
2380 case 0x418: case 0x518: case 0x618: case 0x718:
2381 case 0x818: case 0x918: case 0xa18: case 0xb18:
2382 case 0xc18: case 0xd18: case 0xe18: case 0xf18:
2388 case 0x0:
2391 case 0x1:
2394 case 0x3:
2397 case 0x4:
2400 case 0x5:
2403 case 0x7:
2406 case 0x8:
2409 case 0x9:
2412 case 0xb:
2422 case 0x008: case 0x108: case 0x208: case 0x308: /* WPACK */
2423 case 0x408: case 0x508: case 0x608: case 0x708:
2424 case 0x808: case 0x908: case 0xa08: case 0xb08:
2425 case 0xc08: case 0xd08: case 0xe08: case 0xf08:
2433 case 0:
2435 case 1:
2441 case 2:
2447 case 3:
2458 case 0x201: case 0x203: case 0x205: case 0x207:
2459 case 0x209: case 0x20b: case 0x20d: case 0x20f:
2460 case 0x211: case 0x213: case 0x215: case 0x217:
2461 case 0x219: case 0x21b: case 0x21d: case 0x21f:
2469 case 0x0: /* TMIA */
2474 case 0x8: /* TMIAPH */
2479 case 0xc: case 0xd: case 0xe: case 0xf: /* TMIAxy */
2518 case 0x0: /* MIA */
2523 case 0x8: /* MIAPH */
2528 case 0xc: /* MIABB */
2529 case 0xd: /* MIABT */
2530 case 0xe: /* MIATB */
2531 case 0xf: /* MIATT */
2774 case 0xe:
2804 case 0:
2812 case 1:
2827 case 2:
2850 case 0:
2855 case 1:
2860 case 2:
2877 case ARM_VFP_FPSID:
2886 case ARM_VFP_FPEXC:
2891 case ARM_VFP_FPINST:
2892 case ARM_VFP_FPINST2:
2899 case ARM_VFP_FPSCR:
2908 case ARM_VFP_MVFR0:
2909 case ARM_VFP_MVFR1:
2936 case ARM_VFP_FPSID:
2937 case ARM_VFP_MVFR0:
2938 case ARM_VFP_MVFR1:
2941 case ARM_VFP_FPSCR:
2946 case ARM_VFP_FPEXC:
2952 case ARM_VFP_FPINST:
2953 case ARM_VFP_FPINST2:
3040 case 16:
3041 case 17:
3045 case 8:
3046 case 9:
3051 case 10:
3052 case 11:
3057 case 20:
3058 case 21:
3059 case 22:
3060 case 23:
3061 case 28:
3062 case 29:
3063 case 30:
3064 case 31:
3082 case 0: /* mac: fd + (fn * fm) */
3087 case 1: /* nmac: fd - (fn * fm) */
3093 case 2: /* msc: -fd + (fn * fm) */
3098 case 3: /* nmsc: -fd - (fn * fm) */
3104 case 4: /* mul: fn * fm */
3107 case 5: /* nmul: -(fn * fm) */
3111 case 6: /* add: fn + fm */
3114 case 7: /* sub: fn - fm */
3117 case 8: /* div: fn / fm */
3120 case 14: /* fconst */
3142 case 15: /* extension space */
3144 case 0: /* cpy */
3147 case 1: /* abs */
3150 case 2: /* neg */
3153 case 3: /* sqrt */
3156 case 8: /* cmp */
3159 case 9: /* cmpe */
3162 case 10: /* cmpz */
3165 case 11: /* cmpez */
3169 case 15: /* single<->double conversion */
3175 case 16: /* fuito */
3178 case 17: /* fsito */
3181 case 20: /* fshto */
3186 case 21: /* fslto */
3191 case 22: /* fuhto */
3196 case 23: /* fulto */
3201 case 24: /* ftoui */
3204 case 25: /* ftouiz */
3207 case 26: /* ftosi */
3210 case 27: /* ftosiz */
3213 case 28: /* ftosh */
3218 case 29: /* ftosl */
3223 case 30: /* ftouh */
3228 case 31: /* ftoul */
3292 case 0xc:
3293 case 0xd:
3543 case 3: /* wfi */
3547 case 2: /* wfe */
3548 case 4: /* sev */
3566 case 0: gen_helper_neon_add_u8(CPU_T001); break;
3567 case 1: gen_helper_neon_add_u16(CPU_T001); break;
3568 case 2: gen_op_addl_T0_T1(); break;
3577 case 0: gen_helper_neon_sub_u8(cpu_T[0], cpu_T[1], cpu_T[0]); break;
3578 case 1: gen_helper_neon_sub_u16(cpu_T[0], cpu_T[1], cpu_T[0]); break;
3579 case 2: gen_op_rsbl_T0_T1(); break;
3598 case 0: \
3601 case 1: \
3604 case 2: \
3607 case 3: \
3610 case 4: \
3613 case 5: \
3621 case 0: \
3624 case 1: \
3627 case 2: \
3630 case 3: \
3633 case 4: \
3636 case 5: \
3699 case 0: gen_helper_neon_unzip_u8(); break;
3700 case 1: gen_helper_neon_zip_u16(); break; /* zip and unzip are the same. */
3701 case 2: /* no-op */; break;
3842 case 0:
3846 case 1:
3850 case 2:
3853 case 3:
3870 case 0:
3874 case 1:
3878 case 2:
3890 case 0:
3893 case 1:
3896 case 2:
3913 case 0:
3916 case 1:
3919 case 2:
3958 case 0: gen_helper_neon_narrow_u8(dest, src); break;
3959 case 1: gen_helper_neon_narrow_u16(dest, src); break;
3960 case 2: tcg_gen_trunc_i64_i32(dest, src); break;
3968 case 0: gen_helper_neon_narrow_sat_s8(dest, cpu_env, src); break;
3969 case 1: gen_helper_neon_narrow_sat_s16(dest, cpu_env, src); break;
3970 case 2: gen_helper_neon_narrow_sat_s32(dest, cpu_env, src); break;
3978 case 0: gen_helper_neon_narrow_sat_u8(dest, cpu_env, src); break;
3979 case 1: gen_helper_neon_narrow_sat_u16(dest, cpu_env, src); break;
3980 case 2: gen_helper_neon_narrow_sat_u32(dest, cpu_env, src); break;
3991 case 1: gen_helper_neon_rshl_u16(var, var, shift); break;
3992 case 2: gen_helper_neon_rshl_u32(var, var, shift); break;
3997 case 1: gen_helper_neon_rshl_s16(var, var, shift); break;
3998 case 2: gen_helper_neon_rshl_s32(var, var, shift); break;
4005 case 1: gen_helper_neon_rshl_u16(var, var, shift); break;
4006 case 2: gen_helper_neon_rshl_u32(var, var, shift); break;
4011 case 1: gen_helper_neon_shl_s16(var, var, shift); break;
4012 case 2: gen_helper_neon_shl_s32(var, var, shift); break;
4023 case 0: gen_helper_neon_widen_u8(dest, src); break;
4024 case 1: gen_helper_neon_widen_u16(dest, src); break;
4025 case 2: tcg_gen_extu_i32_i64(dest, src); break;
4030 case 0: gen_helper_neon_widen_s8(dest, src); break;
4031 case 1: gen_helper_neon_widen_s16(dest, src); break;
4032 case 2: tcg_gen_ext_i32_i64(dest, src); break;
4042 case 0: gen_helper_neon_addl_u16(CPU_V001); break;
4043 case 1: gen_helper_neon_addl_u32(CPU_V001); break;
4044 case 2: tcg_gen_add_i64(CPU_V001); break;
4052 case 0: gen_helper_neon_subl_u16(CPU_V001); break;
4053 case 1: gen_helper_neon_subl_u32(CPU_V001); break;
4054 case 2: tcg_gen_sub_i64(CPU_V001); break;
4062 case 0: gen_helper_neon_negl_u16(var, var); break;
4063 case 1: gen_helper_neon_negl_u32(var, var); break;
4064 case 2: gen_helper_neon_negl_u64(var, var); break;
4072 case 1: gen_helper_neon_addl_saturate_s32(op0, cpu_env, op0, op1); break;
4073 case 2: gen_helper_neon_addl_saturate_s64(op0, cpu_env, op0, op1); break;
4083 case 0: gen_helper_neon_mull_s8(dest, a, b); break;
4084 case 1: gen_helper_neon_mull_u8(dest, a, b); break;
4085 case 2: gen_helper_neon_mull_s16(dest, a, b); break;
4086 case 3: gen_helper_neon_mull_u16(dest, a, b); break;
4087 case 4:
4091 case 5:
4144 case 1: /* VQADD */
4151 case 5: /* VQSUB */
4158 case 8: /* VSHL */
4165 case 9: /* VQSHL */
4174 case 10: /* VRSHL */
4181 case 11: /* VQRSHL */
4190 case 16:
4205 case 8: /* VSHL */
4206 case 9: /* VQSHL */
4207 case 10: /* VRSHL */
4208 case 11: /* VQRSHL */
4218 case 20: /* VPMAX */
4219 case 21: /* VPMIN */
4220 case 23: /* VPADD */
4223 case 26: /* VPADD (float) */
4226 case 30: /* VPMIN/VPMAX (float) */
4254 case 0: /* VHADD */
4257 case 1: /* VQADD */
4260 case 2: /* VRHADD */
4263 case 3: /* Logic ops. */
4265 case 0: /* VAND */
4268 case 1: /* BIC */
4271 case 2: /* VORR */
4274 case 3: /* VORN */
4278 case 4: /* VEOR */
4281 case 5: /* VBSL */
4286 case 6: /* VBIT */
4291 case 7: /* VBIF */
4298 case 4: /* VHSUB */
4301 case 5: /* VQSUB */
4304 case 6: /* VCGT */
4307 case 7: /* VCGE */
4310 case 8: /* VSHL */
4313 case 9: /* VQSHL */
4316 case 10: /* VRSHL */
4319 case 11: /* VQRSHL */
4322 case 12: /* VMAX */
4325 case 13: /* VMIN */
4328 case 14: /* VABD */
4331 case 15: /* VABA */
4336 case 16:
4342 case 0: gen_helper_neon_sub_u8(CPU_T001); break;
4343 case 1: gen_helper_neon_sub_u16(CPU_T001); break;
4344 case 2: gen_op_subl_T0_T1(); break;
4349 case 17:
4352 case 0: gen_helper_neon_tst_u8(CPU_T001); break;
4353 case 1: gen_helper_neon_tst_u16(CPU_T001); break;
4354 case 2: gen_helper_neon_tst_u32(CPU_T001); break;
4359 case 0: gen_helper_neon_ceq_u8(CPU_T001); break;
4360 case 1: gen_helper_neon_ceq_u16(CPU_T001); break;
4361 case 2: gen_helper_neon_ceq_u32(CPU_T001); break;
4366 case 18: /* Multiply. */
4368 case 0: gen_helper_neon_mul_u8(CPU_T001); break;
4369 case 1: gen_helper_neon_mul_u16(CPU_T001); break;
4370 case 2: gen_op_mul_T0_T1(); break;
4380 case 19: /* VMUL */
4385 case 0: gen_helper_neon_mul_u8(CPU_T001); break;
4386 case 1: gen_helper_neon_mul_u16(CPU_T001); break;
4387 case 2: gen_op_mul_T0_T1(); break;
4392 case 20: /* VPMAX */
4395 case 21: /* VPMIN */
4398 case 22: /* Hultiply high. */
4401 case 1: gen_helper_neon_qdmulh_s16(CPU_T0E01); break;
4402 case 2: gen_helper_neon_qdmulh_s32(CPU_T0E01); break;
4407 case 1: gen_helper_neon_qrdmulh_s16(CPU_T0E01); break;
4408 case 2: gen_helper_neon_qrdmulh_s32(CPU_T0E01); break;
4413 case 23: /* VPADD */
4417 case 0: gen_helper_neon_padd_u8(CPU_T001); break;
4418 case 1: gen_helper_neon_padd_u16(CPU_T001); break;
4419 case 2: gen_op_addl_T0_T1(); break;
4423 case 26: /* Floating point arithnetic. */
4425 case 0: /* VADD */
4428 case 2: /* VSUB */
4431 case 4: /* VPADD */
4434 case 6: /* VABD */
4441 case 27: /* Float multiply. */
4452 case 28: /* Float compare. */
4462 case 29: /* Float compare absolute. */
4470 case 30: /* Float min/max. */
4476 case 31:
4530 case 0:
4535 case 1:
4539 case 2:
4540 case 3:
4552 case 0: /* VSHR */
4553 case 1: /* VSRA */
4559 case 2: /* VRSHR */
4560 case 3: /* VRSRA */
4566 case 4: /* VSRI */
4571 case 5: /* VSHL, VSLI */
4574 case 6: /* VQSHL */
4580 case 7: /* VQSHLU */
4598 case 0: /* VSHR */
4599 case 1: /* VSRA */
4602 case 2: /* VRSHR */
4603 case 3: /* VRSRA */
4606 case 4: /* VSRI */
4611 case 5: /* VSHL, VSLI */
4613 case 0: gen_helper_neon_shl_u8(CPU_T001); break;
4614 case 1: gen_helper_neon_shl_u16(CPU_T001); break;
4615 case 2: gen_helper_neon_shl_u32(CPU_T001); break;
4619 case 6: /* VQSHL */
4622 case 7: /* VQSHLU */
4624 case 0: gen_helper_neon_qshl_u8(CPU_T0E01); break;
4625 case 1: gen_helper_neon_qshl_u16(CPU_T0E01); break;
4626 case 2: gen_helper_neon_qshl_u32(CPU_T0E01); break;
4639 case 0:
4647 case 1:
4654 case 2:
4677 case 1:
4683 case 2:
4688 case 3:
4793 case 0: case 1:
4796 case 2: case 3:
4799 case 4: case 5:
4802 case 6: case 7:
4805 case 8: case 9:
4808 case 10: case 11:
4811 case 12:
4814 case 13:
4817 case 14:
4822 case 15:
4938 case 0: case 1: case 4: /* VADDL, VADDW, VADDHN, VRADDHN */
4941 case 2: case 3: case 6: /* VSUBL, VSUBW, VSUBHL, VRSUBHL */
4944 case 5: case 7: /* VABAL, VABDL */
4946 case 0:
4949 case 1:
4952 case 2:
4955 case 3:
4958 case 4:
4961 case 5:
4969 case 8: case 9: case 10: case 11: case 12: case 13:
4973 case 14: /* Polynomial VMULL */
4990 case 5: case 8: case 10: /* VABAL, VMLAL, VMLSL */
4993 case 9: case 11: /* VQDMLAL, VQDMLSL */
4998 case 13: /* VQDMULL */
5010 case 0:
5013 case 1:
5016 case 2:
5024 case 0:
5027 case 1:
5030 case 2:
5052 case 0: /* Integer VMLA scalar */
5053 case 1: /* Float VMLA scalar */
5054 case 4: /* Integer VMLS scalar */
5055 case 5: /* Floating point VMLS scalar */
5056 case 8: /* Integer VMUL scalar */
5057 case 9: /* Floating point VMUL scalar */
5058 case 12: /* VQDMULH scalar */
5059 case 13: /* VQRDMULH scalar */
5082 case 0: gen_helper_neon_mul_u8(CPU_T001); break;
5083 case
5084 case 2: gen_op_mul_T0_T1(); break;
5092 case 0:
5095 case 1:
5098 case 4:
5101 case 5:
5111 case 2: /* VMLAL sclar */
5112 case 3: /* VQDMLAL scalar */
5113 case 6: /* VMLSL scalar */
5114 case 7: /* VQDMLSL scalar */
5115 case 10: /* VMULL scalar */
5116 case 11: /* VQDMULL scalar */
5140 case 2: case 6:
5143 case 3: case 7:
5147 case 10:
5150 case 11:
5220 case 0: /* VREV64 */
5227 case 0: tcg_gen_bswap32_i32(cpu_T[0], cpu_T[0]); break;
5228 case 1: gen_swap_half(cpu_T[0]); break;
5229 case 2: /* no-op */ break;
5238 case 0: tcg_gen_bswap32_i32(cpu_T[0], cpu_T[0]); break;
5239 case 1: gen_swap_half(cpu_T[0]); break;
5246 case 4: case 5: /* VPADDL */
5247 case 12: case 13: /* VPADAL */
5256 case 0: gen_helper_neon_paddl_u16(CPU_V001); break;
5257 case 1: gen_helper_neon_paddl_u32(CPU_V001); break;
5258 case 2: tcg_gen_add_i64(CPU_V001); break;
5269 case 33: /* VTRN */
5281 case 34: /* VUZP */
5308 case 35: /* VZIP */
5320 case 0: gen_helper_neon_zip_u8(); break;
5321 case 1: gen_helper_neon_zip_u16(); break;
5322 case 2: /* no-op */; break;
5334 case 36: case 37: /* VMOVN, VQMOVUN, VQMOVN */
5356 case 38: /* VSHLL */
5378 case 1: /* VREV32 */
5380 case 0: tcg_gen_bswap32_i32(cpu_T[0], cpu_T[0]); break;
5381 case 1: gen_swap_half(cpu_T[0]); break;
5385 case 2: /* VREV16 */
5390 case 8: /* CLS */
5392 case 0: gen_helper_neon_cls_s8(cpu_T[0], cpu_T[0]); break;
5393 case 1: gen_helper_neon_cls_s16(cpu_T[0], cpu_T[0]); break;
5394 case 2: gen_helper_neon_cls_s32(cpu_T[0], cpu_T[0]); break;
5398 case 9: /* CLZ */
5400 case 0: gen_helper_neon_clz_u8(cpu_T[0], cpu_T[0]); break;
5401 case 1: gen_helper_neon_clz_u16(cpu_T[0], cpu_T[0]); break;
5402 case 2: gen_helper_clz(cpu_T[0], cpu_T[0]); break;
5406 case 10: /* CNT */
5411 case 11: /* VNOT */
5416 case 14: /* VQABS */
5418 case 0: gen_helper_neon_qabs_s8(cpu_T[0], cpu_env, cpu_T[0]); break;
5419 case 1: gen_helper_neon_qabs_s16(cpu_T[0], cpu_env, cpu_T[0]); break;
5420 case 2: gen_helper_neon_qabs_s32(cpu_T[0], cpu_env, cpu_T[0]); break;
5424 case 15: /* VQNEG */
5426 case 0: gen_helper_neon_qneg_s8(cpu_T[0], cpu_env, cpu_T[0]); break;
5427 case 1: gen_helper_neon_qneg_s16(cpu_T[0], cpu_env, cpu_T[0]); break;
5428 case 2: gen_helper_neon_qneg_s32(cpu_T[0], cpu_env, cpu_T[0]); break;
5432 case 16: case 19: /* VCGT #0, VCLE #0 */
5435 case 0: gen_helper_neon_cgt_s8(CPU_T001); break;
5436 case 1: gen_helper_neon_cgt_s16(CPU_T001); break;
5437 case 2: gen_helper_neon_cgt_s32(CPU_T001); break;
5443 case 17: case 20: /* VCGE #0, VCLT #0 */
5446 case 0: gen_helper_neon_cge_s8(CPU_T001); break;
5447 case 1: gen_helper_neon_cge_s16(CPU_T001); break;
5448 case 2: gen_helper_neon_cge_s32(CPU_T001); break;
5454 case 18: /* VCEQ #0 */
5457 case 0: gen_helper_neon_ceq_u8(CPU_T001); break;
5458 case 1: gen_helper_neon_ceq_u16(CPU_T001); break;
5459 case 2: gen_helper_neon_ceq_u32(CPU_T001); break;
5463 case 22: /* VABS */
5465 case 0: gen_helper_neon_abs_s8(cpu_T[0], cpu_T[0]); break;
5466 case 1: gen_helper_neon_abs_s16(cpu_T[0], cpu_T[0]); break;
5467 case 2: tcg_gen_abs_i32(cpu_T[0], cpu_T[0]); break;
5471 case 23: /* VNEG */
5477 case 24: case 27: /* Float VCGT #0, Float VCLE #0 */
5483 case 25: case 28: /* Float VCGE #0, Float VCLT #0 */
5489 case 26: /* Float VCEQ #0 */
5493 case 30: /* Float VABS */
5496 case 31: /* Float VNEG */
5499 case 32: /* VSWP */
5503 case 33: /* VTRN */
5506 case 0: gen_helper_neon_trn_u8(); break;
5507 case 1: gen_helper_neon_trn_u16(); break;
5508 case 2: abort();
5513 case 56: /* Integer VRECPE */
5516 case 57: /* Integer VRSQRTE */
5519 case 58: /* Float VRECPE */
5522 case 59: /* Float VRSQRTE */
5525 case 60: /* VCVT.F32.S32 */
5528 case 61: /* VCVT.F32.U32 */
5531 case 62: /* VCVT.S32.F32 */
5534 case 63: /* VCVT.U32.F32 */
5676 case 0:
5677 case 1:
5684 case 10:
5685 case 11:
5687 case 14:
5696 case 15:
5876 case 1: /* clrex */
5880 case 4: /* dsb */
5881 case 5: /* dmb */
5882 case 6: /* isb */
5904 case 0: offset = -4; break; /* DA */
5905 case 1: offset = -8; break; /* DB */
5906 case 2: offset = 0; break; /* IA */
5907 case 3: offset = 4; break; /* IB */
5921 case 0: offset = -8; break;
5922 case 1: offset = -4; break;
5923 case 2: offset = 4; break;
5924 case 3: offset = 0; break;
5947 case 0: offset = -4; break; /* DA */
5948 case 1: offset = -8; break; /* DB */
5949 case 2: offset = 0; break; /* IA */
5950 case 3: offset = 4; break; /* IB */
5962 case 0: offset = -8; break;
5963 case 1: offset = -4; break;
5964 case 2: offset = 4; break;
5965 case 3: offset = 0; break;
6091 case 0x0: /* move program status register */
6112 case 0x1:
6127 case 0x2:
6137 case 0x3:
6148 case 0x5: /* saturating add/subtract */
6162 case 7: /* bkpt */
6168 case 0x8: /* signed multiply */
6169 case 0xa:
6170 case 0xc:
6171 case 0xe:
6262 case 0x00:
6269 case 0x01:
6276 case 0x02:
6293 case 0x03:
6301 case 0x04:
6309 case 0x05:
6317 case 0x06:
6325 case 0x07:
6333 case 0x08:
6340 case 0x09:
6347 case 0x0a:
6353 case 0x0b:
6359 case 0x0c:
6366 case 0x0d:
6380 case 0x0e:
6388 case 0x0f:
6403 case 0x0:
6404 case 0x1:
6415 case 0: case 1: case 2: case 3: case 6:
6472 case 0: /* ldrex */
6475 case 1: /* ldrexd */
6482 case 2: /* ldrexb */
6485 case 3: /* ldrexh */
6500 case 0: /* strex */
6503 case 1: /* strexd */
6509 case 2: /* strexb */
6512 case 3: /* strexh */
6554 case 1:
6557 case 2:
6561 case 3:
6612 case 0x4:
6613 case 0x5:
6615 case 0x6:
6616 case 0x7:
6625 case 0: /* Parallel add/subtract. */
6636 case 1:
6708 case 0: gen_sxtb16(tmp); break;
6709 case 2: gen_sxtb(tmp); break;
6710 case 3: gen_sxth(tmp); break;
6711 case 4: gen_uxtb16(tmp); break;
6712 case 6: gen_uxtb(tmp); break;
6713 case 7: gen_uxth(tmp); break;
6747 case 2: /* Multiplies (Type 3). */
6798 case 3:
6801 case 0: /* Unsigned sum of absolute differences. */
6814 case 0x20: case 0x24: case 0x28: case 0x2c:
6833 case 0x12: case 0x16: case 0x1a: case 0x1e: /* sbfx */
6834 case 0x32: case 0x36: case 0x3a: case 0x3e: /* ubfx */
6905 case 0x08:
6906 case 0x09:
6931 /* XXX: test invalid n == 0 case ? */
6969 /* special case: r15 = PC + 8 */
7022 case 0xa:
7023 case 0xb:
7038 case 0xc:
7039 case 0xd:
7040 case 0xe:
7045 case 0xf:
7081 case 0: /* and */
7085 case 1: /* bic */
7089 case 2: /* orr */
7093 case 3: /* orn */
7098 case 4: /* eor */
7102 case 8: /* add */
7108 case 10: /* adc */
7114 case 11: /* sbc */
7120 case 13: /* sub */
7126 case 14: /* rsb */
7191 16-bit instructions in case the second half causes an
7224 case 0: case 1: case 2: case 3:
7227 case 4:
7323 case 0:
7326 case 1:
7329 case 3:
7346 case 0:
7349 case 1:
7352 case 3:
7472 case 5: /* Data processing register constant shift. */
7489 case 13: /* Misc data processing. */
7494 case 0: /* Register controlled shift. */
7506 case 1: /* Sign/zero extend. */
7515 case 0: gen_sxth(tmp); break;
7516 case 1: gen_uxth(tmp); break;
7517 case 2: gen_sxtb16(tmp); break;
7518 case 3: gen_uxtb16(tmp); break;
7519 case 4: gen_sxtb(tmp); break;
7520 case 5: gen_uxtb(tmp); break;
7534 case 2: /* SIMD add/subtract. */
7545 case 3: /* Other data processing. */
7561 case 0x0a: /* rbit */
7564 case 0x08: /* rev */
7567 case 0x09: /* rev16 */
7570 case 0x0b: /* revsh */
7573 case 0x10: /* sel */
7581 case 0x18: /* clz */
7590 case 4: case 5: /* 32-bit multiply. Sum of absolute differences. */
7595 case 0: /* 32 x 32 -> 32 */
7607 case 1: /* 16 x 16 -> 32 */
7616 case 2: /* Dual multiply add. */
7617 case 4: /* Dual multiply subtract. */
7635 case 3: /* 32 * 16 -> 32msb */
7651 case 5: case 6: /* 32 * 32 -> 32msb */
7670 case 7: /* Unsigned sum of absolute differences. */
7682 case 6: case 7: /* 64-bit multiply, Divide. */
7743 case 6: case 7: case 14: case 15:
7757 case 8: case 9: case 10: case 11:
7798 case 0: /* msr cpsr. */
7807 case 1: /* msr spsr. */
7816 case 2: /* cps, nop-hint. */
7844 case 3: /* Special control operations. */
7847 case 2: /* clrex */
7850 case 4: /* dsb */
7851 case 5: /* dmb */
7852 case 6: /* isb */
7860 case 4: /* bxj */
7865 case 5: /* Exception return. */
7868 case 6: /* mrs cpsr. */
7878 case 7: /* mrs spsr. */
7926 case 2: /* Signed bitfield extract. */
7933 case 6: /* Unsigned bitfield extract. */
7940 case 3: /* Bitfield insert/clear. */
7950 case 7:
8018 case 0: /* XY */
8021 case 1: /* 00XY00XY */
8024 case 2: /* XY00XY00 */
8028 case 3: /* XYXYXYXY */
8056 case 12: /* Load/store single data item. */
8087 case 0: case 8: /* Shifted Register. */
8097 case 4: /* Negative offset. */
8100 case 6: /* User privilege. */
8104 case 1: /* Post-decrement. */
8107 case 3: /* Post-increment. */
8111 case 5: /* Pre-decrement. */
8114 case 7: /* Pre-increment. */
8132 case 0: tmp = gen_ld8u(addr, user); break;
8133 case 4: tmp = gen_ld8s(addr, user); break;
8134 case 1: tmp = gen_ld16u(addr, user); break;
8135 case 5: tmp = gen_ld16s(addr, user); break;
8136 case 2: tmp = gen_ld32(addr, user); break;
8151 case 0: gen_st8(tmp, addr, user); break;
8152 case 1: gen_st16(tmp, addr, user); break;
8153 case 2: gen_st32(tmp, addr, user); break;
8218 case 0: case 1:
8256 case 2: case 3:
8267 case 0: /* mov */
8271 case 1: /* cmp */
8274 case 2: /* add */
8280 case 3: /* sub */
8290 case 4:
8309 case 0: /* add */
8315 case 1: /* cmp */
8320 case 2: /* mov/cpy */
8324 case 3:/* branch [and link] exchange thumb register */
8359 case 0x0: /* and */
8364 case 0x1: /* eor */
8369 case 0x2: /* lsl */
8377 case 0x3: /* lsr */
8385 case 0x4: /* asr */
8393 case 0x5: /* adc */
8399 case 0x6: /* sbc */
8405 case 0x7: /* ror */
8413 case 0x8: /* tst */
8418 case 0x9: /* neg */
8424 case 0xa: /* cmp */
8428 case 0xb: /* cmn */
8432 case 0xc: /* orr */
8437 case 0xd: /* mul */
8442 case 0xe: /* bic */
8447 case 0xf: /* mvn */
8463 case 5:
8478 case 0: /* str */
8481 case 1: /* strh */
8484 case 2: /* strb */
8487 case 3: /* ldrsb */
8490 case 4: /* ldr */
8493 case 5: /* ldrh */
8496 case 6: /* ldrb */
8499 case 7: /* ldrsh */
8508 case 6:
8528 case 7:
8548 case 8:
8568 case 9:
8587 case 10:
8603 case 11:
8607 case 0:
8617 case 2: /* sign/zero extend. */
8623 case 0: gen_sxth(tmp); break;
8624 case 1: gen_sxtb(tmp); break;
8625 case 2: gen_uxth(tmp); break;
8626 case 3: gen_uxtb(tmp); break;
8630 case 4: case 5: case 0xc: case 0xd:
8683 case 1: case 3: case 9: case 11: /* czb */
8699 case 15: /* IT, nop-hint. */
8710 case 0xe: /* bkpt */
8717 case 0xa: /* rev */
8723 case 0: tcg_gen_bswap32_i32(tmp, tmp); break;
8724 case 1: gen_rev16(tmp); break;
8725 case 3: gen_revsh(tmp); break;
8731 case 6: /* cps */
8765 case 12:
8792 case 13:
8818 case 14:
8831 case 15:
9063 case DISAS_NEXT:
9067 case DISAS_JUMP:
9068 case DISAS_UPDATE:
9072 case DISAS_TB_JUMP:
9075 case DISAS_WFI:
9078 case DISAS_SWI:
