Lines Matching full:mask
61 int condexec_mask_prev; /* mask at start of instruction/block */
265 #define gen_set_cpsr(var, mask) gen_helper_cpsr_write(var, tcg_const_i32(mask))
317 static void gen_ubfx(TCGv var, int shift, uint32_t mask)
321 tcg_gen_andi_i32(var, var, mask);
340 static void gen_bfi(TCGv dest, TCGv base, TCGv val, int shift, uint32_t mask)
342 tcg_gen_andi_i32(val, val, mask);
344 tcg_gen_andi_i32(base, base, ~(mask << shift));
1435 static inline void gen_op_iwmmxt_extru_T0_M0(int shift, uint32_t mask)
1439 if (mask != ~0u)
1440 tcg_gen_andi_i32(cpu_T[0], cpu_T[0], mask);
1519 static inline int gen_iwmmxt_shift(uint32_t insn, uint32_t mask)
1531 gen_op_movl_T1_im(mask);
3454 /* Return the mask of PSR bits set by a MSR instruction. */
3456 uint32_t mask;
3458 mask = 0;
3460 mask |= 0xff;
3462 mask |= 0xff00;
3464 mask |= 0xff0000;
3466 mask |= 0xff000000;
3468 /* Mask out undefined bits. */
3469 mask &= ~CPSR_RESERVED;
3471 mask &= ~(CPSR_E | CPSR_GE);
3473 mask &= ~CPSR_IT;
3474 /* Mask out execution state bits. */
3476 mask &= ~CPSR_EXEC;
3477 /* Mask out privileged bits. */
3479 mask &= CPSR_USER;
3480 return mask;
3484 static int gen_set_psr_T0(DisasContext *s, uint32_t mask, int spsr)
3493 tcg_gen_andi_i32(tmp, tmp, ~mask);
3494 tcg_gen_andi_i32(cpu_T[0], cpu_T[0], mask);
3498 gen_set_cpsr(cpu_T[0], mask);
6003 uint32_t mask;
6008 mask = val = 0;
6011 mask |= CPSR_A;
6013 mask |= CPSR_I;
6015 mask |= CPSR_F;
6017 val |= mask;
6020 mask |= CPSR_M;
6023 if (mask) {
6025 gen_set_psr_T0(s, mask, 0);
