Lines Matching full:val
339 /* Bitfield insertion. Insert val into base. Clobbers base and val. */
340 static void gen_bfi(TCGv dest, TCGv base, TCGv val, int shift, uint32_t mask)
342 tcg_gen_andi_i32(val, val, mask);
343 tcg_gen_shli_i32(val, val, shift);
345 tcg_gen_or_i32(dest, base, val);
899 static inline void gen_st8(TCGv val, TCGv addr, int index)
901 tcg_gen_qemu_st8(val, addr, index);
902 dead_tmp(val);
904 static inline void gen_st16(TCGv val, TCGv addr, int index)
906 tcg_gen_qemu_st16(val, addr, index);
907 dead_tmp(val);
909 static inline void gen_st32(TCGv val, TCGv addr, int index)
911 tcg_gen_qemu_st32(val, addr, index);
912 dead_tmp(val);
930 static inline void gen_set_pc_im(uint32_t val)
933 tcg_gen_movi_i32(tmp, val);
974 int val, rm, shift, shiftop;
979 val = insn & 0xfff;
981 val = -val;
982 if (val != 0)
983 tcg_gen_addi_i32(var, var, val);
1002 int val, rm;
1007 val = (insn & 0xf) | ((insn >> 4) & 0xf0);
1009 val = -val;
1010 val += extra;
1011 if (val != 0)
1012 tcg_gen_addi_i32(var, var, val);
3528 uint32_t val = (s->condexec_cond << 4) | (s->condexec_mask >> 1);
3530 tcg_gen_movi_i32(tmp, val);
3540 static void gen_nop_hint(DisasContext *s, int val)
3542 switch (val) {
4847 uint32_t val;
4848 val = 0;
4851 val |= 0xff << (n * 8);
4853 tcg_gen_movi_i32(tmp, val);
5706 /* Store a 64-bit value to a register pair. Clobbers val. */
5707 static void gen_storeq_reg(DisasContext *s, int rlow, int rhigh, TCGv_i64 val)
5711 tcg_gen_trunc_i64_i32(tmp, val);
5714 tcg_gen_shri_i64(val, val, 32);
5715 tcg_gen_trunc_i64_i32(tmp, val);
5720 static void gen_addq_lo(DisasContext *s, TCGv_i64 val, int rlow)
5730 tcg_gen_add_i64(val, val, tmp);
5734 static void gen_addq(DisasContext *s, TCGv_i64 val, int rlow, int rhigh)
5747 tcg_gen_add_i64(val, val, tmp);
5751 static void gen_logicq_cc(TCGv_i64 val)
5754 gen_helper_logicq_cc(tmp, val);
5800 unsigned int cond, insn, val, op1, i, shift, rm, rs, rn, rd, sh;
5979 val = (uint32_t)s->pc;
5981 tcg_gen_movi_i32(tmp, val);
5986 val += (offset << 2) | ((insn >> 23) & 2) | 1;
5988 val += 4;
5989 gen_bx_im(s, val);
6004 uint32_t val;
6008 mask = val = 0;
6017 val |= mask;
6021 val |= (insn & 0x1f);
6024 gen_op_movl_T0_im(val);
6055 val = ((insn >> 4) & 0xf000) | (insn & 0xfff);
6059 tcg_gen_movi_i32(tmp, val);
6064 tcg_gen_ori_i32(tmp, tmp, val << 16);
6074 val = insn & 0xff;
6077 val = (val >> shift) | (val << (32 - shift));
6078 gen_op_movl_T0_im(val);
6230 val = insn & 0xff;
6233 val = (val >> shift) | (val << (32 - shift));
6236 tcg_gen_movi_i32(tmp2, val);
6970 val = (long)s->pc + 4;
6972 tcg_gen_movi_i32(tmp, val);
7027 val = (int32_t)s->pc;
7030 tcg_gen_movi_i32(tmp, val);
7034 val += (offset << 2) + 4;
7035 gen_jmp(s, val);
8176 uint32_t val, insn, op, rm, rn, rd, shift, cond;
8294 val = s->pc + 2 + ((insn & 0xff) * 4);
8295 val &= ~(uint32_t)2;
8297 tcg_gen_movi_i32(addr, val);
8327 val = (uint32_t)s->pc | 1;
8329 tcg_gen_movi_i32(tmp2, val);
8344 val = rm;
8346 rd = val;
8347 val = 1;
8349 val = 0;
8451 val = 1;
8456 if (val)
8513 val = (insn >> 4) & 0x7c;
8514 tcg_gen_addi_i32(addr, addr, val);
8533 val = (insn >> 6) & 0x1f;
8534 tcg_gen_addi_i32(addr, addr, val);
8553 val = (insn >> 5) & 0x3e;
8554 tcg_gen_addi_i32(addr, addr, val);
8572 val = (insn & 0xff) * 4;
8573 tcg_gen_addi_i32(addr, addr, val);
8598 val = (insn & 0xff) * 4;
8599 tcg_gen_addi_i32(tmp, tmp, val);
8610 val = (insn & 0x7f) * 4;
8612 val = -(int32_t)val;
8613 tcg_gen_addi_i32(tmp, tmp, val);
8694 val = (uint32_t)s->pc + 2;
8695 val += offset;
8696 gen_jmp(s, val);
8754 val = ((insn & 7) << 6) & shift;
8755 gen_op_movl_T0_im(val);
8812 val = (uint32_t)s->pc + 2;
8814 val += offset << 1;
8815 gen_jmp(s, val);
8825 val = (uint32_t)s->pc;
8827 val += (offset << 1) + 2;
8828 gen_jmp(s, val);
