Lines Matching refs:t1
126 cpu_T[1] = tcg_global_reg_new_i32(TCG_AREG2, "T1");
423 /* Dual 16-bit add. Result placed in t0 and t1 is marked as dead.
424 tmp = (t0 ^ t1) & 0x8000;
426 t1 &= ~0x8000;
427 t0 = (t0 + t1) ^ tmp;
430 static void gen_add16(TCGv t0, TCGv t1)
433 tcg_gen_xor_i32(tmp, t0, t1);
436 tcg_gen_andi_i32(t1, t1, ~0x8000);
437 tcg_gen_add_i32(t0, t0, t1);
440 dead_tmp(t1);
461 /* T0 += T1 + CF. */
471 /* dest = T0 + T1 + CF. */
472 static void gen_add_carry(TCGv dest, TCGv t0, TCGv t1)
475 tcg_gen_add_i32(dest, t0, t1);
481 /* dest = T0 - T1 + CF - 1. */
482 static void gen_sub_carry(TCGv dest, TCGv t0, TCGv t1)
485 tcg_gen_sub_i32(dest, t0, t1);
495 /* T0 &= ~T1. Clobbers T1. */
497 static inline void tcg_gen_bic_i32(TCGv dest, TCGv t0, TCGv t1)
500 tcg_gen_not_i32(tmp, t1);
511 #define tcg_gen_abs_i32(t0, t1) gen_helper_abs(t0, t1)
514 static void tcg_gen_rori_i32(TCGv t0, TCGv t1, int i)
522 tcg_gen_shri_i32(tmp, t1, i);
523 tcg_gen_shli_i32(t1, t1, 32 - i);
524 tcg_gen_or_i32(t0, t1, tmp);
3441 static inline void gen_mulxy(TCGv t0, TCGv t1, int x, int y)
3448 tcg_gen_sari_i32(t1, t1, 16);
3450 gen_sxth(t1);
3451 tcg_gen_mul_i32(t0, t0, t1);
3557 T0/T1 are removed. */
4243 NEON_GET_REG(T1, rn, n + 1);
4246 NEON_GET_REG(T1, rm, n + 1);
4251 NEON_GET_REG(T1, rm, pass);
4333 NEON_GET_REG(T1, rd, pass);
4373 NEON_GET_REG(T1, rd, pass);
4444 NEON_GET_REG(T1, rd, pass);
4594 /* Operands in T0 and T1. */
4634 NEON_GET_REG(T1, rd, pass);
5065 NEON_GET_REG(T1, rn, pass);
5090 NEON_GET_REG(T1, rd, pass);
5121 NEON_GET_REG(T1, rn, 1);
5225 NEON_GET_REG(T1, rm, pass * 2 + 1);
5234 NEON_SET_REG(T1, rd, pass * 2);
5273 NEON_GET_REG(T1, rd, n + 1);
5274 NEON_SET_REG(T1, rm, n);
5318 NEON_GET_REG(T1, rd, n);
5500 NEON_GET_REG(T1, rd, pass);
5501 NEON_SET_REG(T1, rm, pass);
5504 NEON_GET_REG(T1, rd, pass);
5511 NEON_SET_REG(T1, rm, pass);
7071 to the high bit of T1.
