Lines Matching full:cond
490 int cond = instr & CondMask;
493 if (cond == nv) {
502 switch (cond) {
650 Condition cond = static_cast<Condition>(instr & CondMask);
652 ldr(rd, MemOperand(pc, 0), cond);
654 ldr(ip, MemOperand(pc, 0), cond);
818 void Assembler::b(int branch_offset, Condition cond) {
822 emit(cond | B27 | B25 | (imm24 & Imm24Mask));
824 if (cond == al)
830 void Assembler::bl(int branch_offset, Condition cond) {
834 emit(cond | B27 | B25 | B24 | (imm24 & Imm24Mask));
848 void Assembler::blx(Register target, Condition cond) { // v5 and above
851 emit(cond | B24 | B21 | 15*B16 | 15*B12 | 15*B8 | 3*B4 | target.code());
855 void Assembler::bx(Register target, Condition cond) { // v5 and above, plus v4t
858 emit(cond | B24 | B21 | 15*B16 | 15*B12 | 15*B8 | B4 | target.code());
866 // cond(31-28) | 01111(27-23)| 1(22) | 1(21) | widthm1(20-16) |
869 const Operand& src3, Condition cond) {
873 emit(cond | 0x3F*B21 | src3.imm32_*B16 |
879 SBit s, Condition cond) {
880 addrmod1(cond | 0*B21 | s, src1, dst, src2);
885 SBit s, Condition cond) {
886 addrmod1(cond | 1*B21 | s, src1, dst, src2);
891 SBit s, Condition cond) {
892 addrmod1(cond | 2*B21 | s, src1, dst, src2);
897 SBit s, Condition cond) {
898 addrmod1(cond | 3*B21 | s, src1, dst, src2);
903 SBit s, Condition cond) {
904 addrmod1(cond | 4*B21 | s, src1, dst, src2);
926 SBit s, Condition cond) {
927 addrmod1(cond | 5*B21 | s, src1, dst, src2);
932 SBit s, Condition cond) {
933 addrmod1(cond | 6*B21 | s, src1, dst, src2);
938 SBit s, Condition cond) {
939 addrmod1(cond | 7*B21 | s, src1, dst, src2);
943 void Assembler::tst(Register src1, const Operand& src2, Condition cond) {
944 addrmod1(cond | 8*B21 | S, src1, r0, src2);
948 void Assembler::teq(Register src1, const Operand& src2, Condition cond) {
949 addrmod1(cond | 9*B21 | S, src1, r0, src2);
953 void Assembler::cmp(Register src1, const Operand& src2, Condition cond) {
954 addrmod1(cond | 10*B21 | S, src1, r0, src2);
958 void Assembler::cmn(Register src1, const Operand& src2, Condition cond) {
959 addrmod1(cond | 11*B21 | S, src1, r0, src2);
964 SBit s, Condition cond) {
965 addrmod1(cond | 12*B21 | s, src1, dst, src2);
969 void Assembler::mov(Register dst, const Operand& src, SBit s, Condition cond) {
973 addrmod1(cond | 13*B21 | s, r0, dst, src);
978 SBit s, Condition cond) {
979 addrmod1(cond | 14*B21 | s, src1, dst, src2);
983 void Assembler::mvn(Register dst, const Operand& src, SBit s, Condition cond) {
984 addrmod1(cond | 15*B21 | s, r0, dst, src);
990 SBit s, Condition cond) {
992 emit(cond | A | s | dst.code()*B16 | srcA.code()*B12 |
998 SBit s, Condition cond) {
1001 emit(cond | s | dst.code()*B16 | src2.code()*B8 | B7 | B4 | src1.code());
1010 Condition cond) {
1013 emit(cond | B23 | B22 | A | s | dstH.code()*B16 | dstL.code()*B12 |
1023 Condition cond) {
1026 emit(cond | B23 | B22 | s | dstH.code()*B16 | dstL.code()*B12 |
1036 Condition cond) {
1039 emit(cond | B23 | A | s | dstH.code()*B16 | dstL.code()*B12 |
1049 Condition cond) {
1052 emit(cond | B23 | s | dstH.code()*B16 | dstL.code()*B12 |
1058 void Assembler::clz(Register dst, Register src, Condition cond) {
1061 emit(cond | B24 | B22 | B21 | 15*B16 | dst.code()*B12 |
1067 void Assembler::mrs(Register dst, SRegister s, Condition cond) {
1069 emit(cond | B24 | s | 15*B16 | dst.code()*B12);
1074 Condition cond) {
1085 cond);
1086 msr(fields, Operand(ip), cond);
1094 emit(cond | instr | B24 | B21 | fields | 15*B12);
1099 void Assembler::ldr(Register dst, const MemOperand& src, Condition cond) {
1103 addrmod2(cond | B26 | L, dst, src);
1124 void Assembler::str(Register src, const MemOperand& dst, Condition cond) {
1125 addrmod2(cond | B26, src, dst);
1146 void Assembler::ldrb(Register dst, const MemOperand& src, Condition cond) {
1147 addrmod2(cond | B26 | B | L, dst, src);
1151 void Assembler::strb(Register src, const MemOperand& dst, Condition cond) {
1152 addrmod2(cond | B26 | B, src, dst);
1156 void Assembler::ldrh(Register dst, const MemOperand& src, Condition cond) {
1157 addrmod3(cond | L | B7 | H | B4, dst, src);
1161 void Assembler::strh(Register src, const MemOperand& dst, Condition cond) {
1162 addrmod3(cond | B7 | H | B4, src, dst);
1166 void Assembler::ldrsb(Register dst, const MemOperand& src, Condition cond) {
1167 addrmod3(cond | L | B7 | S6 | B4, dst, src);
1171 void Assembler::ldrsh(Register dst, const MemOperand& src, Condition cond) {
1172 addrmod3(cond | L | B7 | S6 | H | B4, dst, src);
1180 Condition cond) {
1184 addrmod4(cond | B27 | am | L, base, dst);
1187 if (cond == al && (dst & pc.bit()) != 0) {
1201 Condition cond) {
1202 addrmod4(cond | B27 | am, base, src);
1207 void Assembler::swp(Register dst, Register src, Register base, Condition cond) {
1210 emit(cond | P | base.code()*B16 | dst.code()*B12 |
1218 Condition cond) {
1221 emit(cond | P | B | base.code()*B16 | dst.code()*B12 |
1245 void Assembler::swi(uint32_t imm24, Condition cond) {
1247 emit(cond | 15*B24 | imm24);
1258 Condition cond) {
1260 emit(cond | B27 | B26 | B25 | (opcode_1 & 15)*B20 | crn.code()*B16 |
1281 Condition cond) {
1283 emit(cond | B27 | B26 | B25 | (opcode_1 & 7)*B21 | crn.code()*B16 |
1304 Condition cond) {
1306 emit(cond | B27 | B26 | B25 | (opcode_1 & 7)*B21 | L | crn.code()*B16 |
1325 Condition cond) {
1326 addrmod5(cond | B27 | B26 | l | L | coproc*B8, crd, src);
1335 Condition cond) {
1338 emit(cond | B27 | B26 | U | l | L | rn.code()*B16 | crd.code()*B12 |
1364 Condition cond) {
1365 addrmod5(cond | B27 | B26 | l | coproc*B8, crd, dst);
1374 Condition cond) {
1377 emit(cond | B27 | B26 | U | l | rn.code()*B16 | crd.code()*B12 |
1403 const Condition cond) {
1406 // cond(31-28) | 1101(27-24)| 1001(23-20) | Rbase(19-16) |
1410 emit(cond | 0xD9*B20 | base.code()*B16 | dst.code()*B12 |
1418 const Condition cond) {
1421 // cond(31-28) | 1101(27-24)| 1000(23-20) | | Rbase(19-16) |
1425 emit(cond | 0xD8*B20 | base.code()*B16 | src.code()*B12 |
1433 const Condition cond) {
1436 // cond(31-28) | 1100(27-24)| 010(23-21) | op=0(20) | Rt2(19-16) |
1440 emit(cond | 0xC*B24 | B22 | src2.code()*B16 |
1448 const Condition cond) {
1451 // cond(31-28) | 1100(27-24)| 010(23-21) | op=1(20) | Rt2(19-16) |
1455 emit(cond | 0xC*B24 | B22 | B20 | dst2.code()*B16 |
1462 const Condition cond) {
1465 // cond(31-28) | 1110(27-24)| 000(23-21) | op=0(20) | Vn(19-16) |
1469 emit(cond | 0xE*B24 | (dst.code() >> 1)*B16 |
1476 const Condition cond) {
1479 // cond(31-28) | 1110(27-24)| 000(23-21) | op=1(20) | Vn(19-16) |
1483 emit(cond | 0xE*B24 | B20 | (src.code() >> 1)*B16 |
1490 const Condition cond) {
1493 // cond(31-28) | 11101(27-23)| D=?(22) | 11(21-20) | 1(19) | opc2=000(18-16) |
1496 emit(cond | 0xE*B24 | B23 | 0x3*B20 | B19 |
1504 const Condition cond) {
1507 // cond(31-28) | 11101(27-23)| D=?(22) | 11(21-20) | 1(19) | opc2=101(18-16)|
1510 emit(cond | 0xE*B24 | B23 |(0x1 & dst.code())*B22 |
1519 const Condition cond) {
1523 // cond(31-28) | 11100(27-23)| D=?(22) | 11(21-20) | Vn(19-16) |
1526 emit(cond | 0xE*B24 | 0x3*B20 | src1.code()*B16 |
1534 const Condition cond) {
1538 // cond(31-28) | 11100(27-23)| D=?(22) | 11(21-20) | Vn(19-16) |
1541 emit(cond | 0xE*B24 | 0x3*B20 | src1.code()*B16 |
1549 const Condition cond) {
1553 // cond(31-28) | 11100(27-23)| D=?(22) | 10(21-20) | Vn(19-16) |
1556 emit(cond | 0xE*B24 | 0x2*B20 | src1.code()*B16 |
1564 const Condition cond) {
1568 // cond(31-28) | 11101(27-23)| D=?(22) | 00(21-20) | Vn(19-16) |
1571 emit(cond | 0xE*B24 | B23 | src1.code()*B16 |
1579 const Condition cond) {
1582 // cond(31-28) | 11101 (27-23)| D=?(22) | 11 (21-20) | 0100 (19-16) |
1585 emit(cond | 0xE*B24 |B23 | 0x3*B20 | B18 |
1590 void Assembler::vmrs(Register dst, Condition cond) {
1592 // cond(31-28) | 1110 (27-24) | 1111(23-20)| 0001 (19-16) |
1595 emit(cond | 0xE*B24 | 0xF*B20 | B16 |
1604 Condition cond) {
1609 mov(dst, Operand(x.rn_), s, cond);
1611 sub(dst, x.rn_, Operand(x.offset_), s, cond);
1613 add(dst, x.rn_, Operand(x.offset_), s, cond);
1620 mov(dst, Operand(x.rn_), s, cond);
1622 sub(dst, x.rn_, Operand(x.rm_, x.shift_op_, x.shift_imm_), s, cond);
1624 add(dst, x.rn_, Operand(x.rm_, x.shift_op_, x.shift_imm_), s, cond);
