Lines Matching defs:op2
230 void emitInst(ARMWord op, int rd, int rn, ARMWord op2)
232 ASSERT ( ((op2 & ~OP2_IMM) <= 0xfff) || (((op2 & ~OP2_IMMh) <= 0xfff)) );
233 m_buffer.putInt(op | RN(rn) | RD(rd) | op2);
236 void and_r(int rd, int rn, ARMWord op2, Condition cc = AL)
238 emitInst(static_cast<ARMWord>(cc) | AND, rd, rn, op2);
241 void ands_r(int rd, int rn, ARMWord op2, Condition cc = AL)
243 emitInst(static_cast<ARMWord>(cc) | AND | SET_CC, rd, rn, op2);
246 void eor_r(int rd, int rn, ARMWord op2, Condition cc = AL)
248 emitInst(static_cast<ARMWord>(cc) | EOR, rd, rn, op2);
251 void eors_r(int rd, int rn, ARMWord op2, Condition cc = AL)
253 emitInst(static_cast<ARMWord>(cc) | EOR | SET_CC, rd, rn, op2);
256 void sub_r(int rd, int rn, ARMWord op2, Condition cc = AL)
258 emitInst(static_cast<ARMWord>(cc) | SUB, rd, rn, op2);
261 void subs_r(int rd, int rn, ARMWord op2, Condition cc = AL)
263 emitInst(static_cast<ARMWord>(cc) | SUB | SET_CC, rd, rn, op2);
266 void rsb_r(int rd, int rn, ARMWord op2, Condition cc = AL)
268 emitInst(static_cast<ARMWord>(cc) | RSB, rd, rn, op2);
271 void rsbs_r(int rd, int rn, ARMWord op2, Condition cc = AL)
273 emitInst(static_cast<ARMWord>(cc) | RSB | SET_CC, rd, rn, op2);
276 void add_r(int rd, int rn, ARMWord op2, Condition cc = AL)
278 emitInst(static_cast<ARMWord>(cc) | ADD, rd, rn, op2);
281 void adds_r(int rd, int rn, ARMWord op2, Condition cc = AL)
283 emitInst(static_cast<ARMWord>(cc) | ADD | SET_CC, rd, rn, op2);
286 void adc_r(int rd, int rn, ARMWord op2, Condition cc = AL)
288 emitInst(static_cast<ARMWord>(cc) | ADC, rd, rn, op2);
291 void adcs_r(int rd, int rn, ARMWord op2, Condition cc = AL)
293 emitInst(static_cast<ARMWord>(cc) | ADC | SET_CC, rd, rn, op2);
296 void sbc_r(int rd, int rn, ARMWord op2, Condition cc = AL)
298 emitInst(static_cast<ARMWord>(cc) | SBC, rd, rn, op2);
301 void sbcs_r(int rd, int rn, ARMWord op2, Condition cc = AL)
303 emitInst(static_cast<ARMWord>(cc) | SBC | SET_CC, rd, rn, op2);
306 void rsc_r(int rd, int rn, ARMWord op2, Condition cc = AL)
308 emitInst(static_cast<ARMWord>(cc) | RSC, rd, rn, op2);
311 void rscs_r(int rd, int rn, ARMWord op2, Condition cc = AL)
313 emitInst(static_cast<ARMWord>(cc) | RSC | SET_CC, rd, rn, op2);
316 void tst_r(int rn, ARMWord op2, Condition cc = AL)
318 emitInst(static_cast<ARMWord>(cc) | TST | SET_CC, 0, rn, op2);
321 void teq_r(int rn, ARMWord op2, Condition cc = AL)
323 emitInst(static_cast<ARMWord>(cc) | TEQ | SET_CC, 0, rn, op2);
326 void cmp_r(int rn, ARMWord op2, Condition cc = AL)
328 emitInst(static_cast<ARMWord>(cc) | CMP | SET_CC, 0, rn, op2);
331 void orr_r(int rd, int rn, ARMWord op2, Condition cc = AL)
333 emitInst(static_cast<ARMWord>(cc) | ORR, rd, rn, op2);
336 void orrs_r(int rd, int rn, ARMWord op2, Condition cc = AL)
338 emitInst(static_cast<ARMWord>(cc) | ORR | SET_CC, rd, rn, op2);
341 void mov_r(int rd, ARMWord op2, Condition cc = AL)
343 emitInst(static_cast<ARMWord>(cc) | MOV, rd, ARMRegisters::r0, op2);
347 void movw_r(int rd, ARMWord op2, Condition cc = AL)
349 ASSERT((op2 | 0xf0fff) == 0xf0fff);
350 m_buffer.putInt(static_cast<ARMWord>(cc) | MOVW | RD(rd) | op2);
353 void movt_r(int rd, ARMWord op2, Condition cc = AL)
355 ASSERT((op2 | 0xf0fff) == 0xf0fff);
356 m_buffer.putInt(static_cast<ARMWord>(cc) | MOVT | RD(rd) | op2);
360 void movs_r(int rd, ARMWord op2, Condition cc = AL)
362 emitInst(static_cast<ARMWord>(cc) | MOV | SET_CC, rd, ARMRegisters::r0, op2);
365 void bic_r(int rd, int rn, ARMWord op2, Condition cc = AL)
367 emitInst(static_cast<ARMWord>(cc) | BIC, rd, rn, op2);
370 void bics_r(int rd, int rn, ARMWord op2, Condition cc = AL)
372 emitInst(static_cast<ARMWord>(cc) | BIC | SET_CC, rd, rn, op2);
375 void mvn_r(int rd, ARMWord op2, Condition cc = AL)
377 emitInst(static_cast<ARMWord>(cc) | MVN, rd, ARMRegisters::r0, op2);
380 void mvns_r(int rd, ARMWord op2, Condition cc = AL)
382 emitInst(static_cast<ARMWord>(cc) | MVN | SET_CC, rd, ARMRegisters::r0, op2);
435 void dtr_u(bool isLoad, int rd, int rb, ARMWord op2, Condition cc = AL)
437 emitInst(static_cast<ARMWord>(cc) | DTR | (isLoad ? DT_LOAD : 0) | DT_UP, rd, rb, op2);
445 void dtr_d(bool isLoad, int rd, int rb, ARMWord op2, Condition cc = AL)
447 emitInst(static_cast<ARMWord>(cc) | DTR | (isLoad ? DT_LOAD : 0), rd, rb, op2);
460 void ldrh_d(int rd, int rb, ARMWord op2, Condition cc = AL)
462 emitInst(static_cast<ARMWord>(cc) | LDRH | HDT_UH | DT_PRE, rd, rb, op2);
465 void ldrh_u(int rd, int rb, ARMWord op2, Condition cc = AL)
467 emitInst(static_cast<ARMWord>(cc) | LDRH | HDT_UH | DT_UP | DT_PRE, rd, rb, op2);
475 void fdtr_u(bool isLoad, int rd, int rb, ARMWord op2, Condition cc = AL)
477 ASSERT(op2 <= 0xff);
478 emitInst(static_cast<ARMWord>(cc) | FDTR | DT_UP | (isLoad ? DT_LOAD : 0), rd, rb, op2);
481 void fdtr_d(bool isLoad, int rd, int rb, ARMWord op2, Condition cc = AL)
483 ASSERT(op2 <= 0xff);
484 emitInst(static_cast<ARMWord>(cc) | FDTR | (isLoad ? DT_LOAD : 0), rd, rb, op2);
