Lines Matching full:mask
31 uint16 intr_en_reg; /* 0x06, Intr mask register */
50 #define SPID_INTR_EN_REG 0x06 /* 16 bits - Interrupt mask */
71 /* Bit mask for SPID_RESPONSE_DELAY device register */
74 /* Bit mask for SPID_STATUS_ENABLE device register */
82 /* Bit mask for SPID_RESET_BP device register */
87 /* Bit mask for SPID_INTR_REG device register */
105 /* Bit mask for 32bit SPID_STATUS_REG device register */
121 /* Bit mask for 16 bits SPID_F1_INFO_REG device register */
126 /* Bit mask for 16 bits SPID_F2_INFO_REG device register */
131 /* Bit mask for 16 bits SPID_F3_INFO_REG device register */
136 /* Bit mask for 32 bits SPID_TEST_READ device register read in 16bit LE mode */
