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224 \&\fITarget \s-1MIPS\s0 options:\fR
796 a \s-1MIPS\s0 processor.
828 Generate code for a particular \s-1MIPS\s0 Instruction Set Architecture level.
835 \&\fB\s-1MIPS\s0 V\fR, \fB\s-1MIPS32\s0\fR, \fB\s-1MIPS32\s0 Release 2\fR, \fB\s-1MIPS64\s0\fR,
840 Generate code for a particular \s-1MIPS\s0 cpu.
843 Schedule and tune for a particular \s-1MIPS\s0 cpu.
883 Generate code for the \s-1MIPS\s0 16 processor. This is equivalent to putting
892 Generate code for the \s-1MIPS\-3D\s0 Application Specific Extension.
893 This tells the assembler to accept \s-1MIPS\-3D\s0 instructions.
948 \&\fBas\fR is configured for is a \s-1MIPS\s0 \s-1ELF\s0 or \s-1ECOFF\s0 target.