1 /**************************************************************************** 2 **+-----------------------------------------------------------------------+** 3 **| |** 4 **| Copyright(c) 1998 - 2008 Texas Instruments. All rights reserved. |** 5 **| All rights reserved. |** 6 **| |** 7 **| Redistribution and use in source and binary forms, with or without |** 8 **| modification, are permitted provided that the following conditions |** 9 **| are met: |** 10 **| |** 11 **| * Redistributions of source code must retain the above copyright |** 12 **| notice, this list of conditions and the following disclaimer. |** 13 **| * Redistributions in binary form must reproduce the above copyright |** 14 **| notice, this list of conditions and the following disclaimer in |** 15 **| the documentation and/or other materials provided with the |** 16 **| distribution. |** 17 **| * Neither the name Texas Instruments nor the names of its |** 18 **| contributors may be used to endorse or promote products derived |** 19 **| from this software without specific prior written permission. |** 20 **| |** 21 **| THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |** 22 **| "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |** 23 **| LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |** 24 **| A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |** 25 **| OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |** 26 **| SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |** 27 **| LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |** 28 **| DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |** 29 **| THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |** 30 **| (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |** 31 **| OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |** 32 **| |** 33 **+-----------------------------------------------------------------------+** 34 ****************************************************************************/ 35 36 #ifndef PUBLIC_HOST_INT_H 37 #define PUBLIC_HOST_INT_H 38 39 #include "public_types.h" 40 41 42 /************************************************************************* 43 44 Host Interrupt Register (WiLink -> Host) 45 46 **************************************************************************/ 47 48 #define ACX_INTR_RX0_DATA BIT_0 /* RX packet is ready in Xfer buffer #0*/ 49 #define ACX_INTR_TX_RESULT BIT_1 /* TX result(s) are in the TX complete buffer */ 50 #define ACX_INTR_TX_XFR BIT_2 /* OBSOLETE*/ 51 #define ACX_INTR_RX1_DATA BIT_3 /* RX packet is ready in Xfer buffer #1*/ 52 #define ACX_INTR_EVENT_A BIT_4 /* Event was entered to Event MBOX #A*/ 53 #define ACX_INTR_EVENT_B BIT_5 /* Event was entered to Event MBOX #B */ 54 #define ACX_INTR_WAKE_ON_HOST BIT_6 /* OBSOLETE */ 55 #define ACX_INTR_TRACE_A BIT_7 /* Trace meassge on MBOX #A*/ 56 #define ACX_INTR_TRACE_B BIT_8 /* Trace meassge on MBOX #B*/ 57 #define ACX_INTR_CMD_COMPLETE BIT_9 /* Command processing completion*/ 58 #define ACX_INTR_INIT_COMPLETE BIT_14 /* Init sequence is done*/ 59 60 #define ACX_INTR_ALL 0xFFFFFFFF 61 62 63 /************************************************************************* 64 65 Interrupt Trigger Register (Host -> WiLink) 66 67 **************************************************************************/ 68 69 /******** Hardware to Embedded CPU Interrupts - first 32-bit register set ********/ 70 71 #define INTR_TRIG_CMD BIT_0 /* Host Command Interrupt. Setting this bit masks*/ 72 /* the interrupt that the host issues to inform*/ 73 /* the FW that it has sent a command*/ 74 /* to the Wlan hardware Command Mailbox.*/ 75 76 #define INTR_TRIG_EVENT_ACK BIT_1 /* Host Event Acknowlegde Interrupt. The host */ 77 /* sets this bit to acknowledge that it received*/ 78 /* the unsolicited information from the event*/ 79 /* mailbox.*/ 80 81 #define INTR_TRIG_TX_PROC0 BIT_2 /* The host sets this bit to inform the Wlan */ 82 /* FW that a TX packet is in the XFER */ 83 /* Buffer #0.*/ 84 85 #define INTR_TRIG_RX_PROC0 BIT_3 /* The host sets this bit to inform the FW */ 86 /* that it read a packet from RX XFER */ 87 /* Buffer #0.*/ 88 89 #define INTR_TRIG_DEBUG_ACK BIT_4 90 91 #define INTR_TRIG_STATE_CHANGED BIT_5 92 93 94 /******** Hardware to Embedded CPU Interrupts - second 32-bit register set ********/ 95 96 #define INTR_TRIG_RX_PROC1 BIT_17 /* The host sets this bit to inform the FW */ 97 /* that it read a packet from RX XFER */ 98 /* Buffer #1. */ 99 100 #define INTR_TRIG_TX_PROC1 BIT_18 /* The host sets this bit to inform the Wlan */ 101 /* hardware that a TX packet is in the XFER */ 102 /* Buffer #1.*/ 103 104 #endif 105 106
