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      1 /*
      2  * Broadcom HND chip & on-chip-interconnect-related definitions.
      3  *
      4  * Copyright (C) 1999-2009, Broadcom Corporation
      5  *
      6  *      Unless you and Broadcom execute a separate written software license
      7  * agreement governing use of this software, this software is licensed to you
      8  * under the terms of the GNU General Public License version 2 (the "GPL"),
      9  * available at http://www.broadcom.com/licenses/GPLv2.php, with the
     10  * following added to such license:
     11  *
     12  *      As a special exception, the copyright holders of this software give you
     13  * permission to link this software with independent modules, and to copy and
     14  * distribute the resulting executable under terms of your choice, provided that
     15  * you also meet, for each linked independent module, the terms and conditions of
     16  * the license of that module.  An independent module is a module which is not
     17  * derived from this software.  The special exception does not apply to any
     18  * modifications of the software.
     19  *
     20  *      Notwithstanding the above, under no circumstances may you combine this
     21  * software in any way with any other Broadcom software provided under a license
     22  * other than the GPL, without Broadcom's express prior written consent.
     23  *
     24  * $Id: hndsoc.h,v 13.3.10.3 2008/08/06 03:43:25 Exp $
     25  */
     26 
     27 #ifndef	_HNDSOC_H
     28 #define	_HNDSOC_H
     29 
     30 /* Include the soci specific files */
     31 #include <sbconfig.h>
     32 #include <aidmp.h>
     33 
     34 /*
     35  * SOC Interconnect Address Map.
     36  * All regions may not exist on all chips.
     37  */
     38 #define SI_SDRAM_BASE		0x00000000	/* Physical SDRAM */
     39 #define SI_PCI_MEM		0x08000000	/* Host Mode sb2pcitranslation0 (64 MB) */
     40 #define SI_PCI_MEM_SZ		(64 * 1024 * 1024)
     41 #define SI_PCI_CFG		0x0c000000	/* Host Mode sb2pcitranslation1 (64 MB) */
     42 #define	SI_SDRAM_SWAPPED	0x10000000	/* Byteswapped Physical SDRAM */
     43 
     44 #define SI_ENUM_BASE    	0x18000000	/* Enumeration space base */
     45 #define SI_CORE_SIZE    	0x1000		/* each core gets 4Kbytes for registers */
     46 #ifndef SI_MAXCORES
     47 #define	SI_MAXCORES		16		/* Max cores (this is arbitrary, for software
     48 						 * convenience and could be changed if we
     49 						 * make any larger chips
     50 						 */
     51 #endif
     52 
     53 #define	SI_FASTRAM		0x19000000	/* On-chip RAM on chips that also have DDR */
     54 
     55 #define	SI_FLASH2		0x1c000000	/* Flash Region 2 (region 1 shadowed here) */
     56 #define	SI_FLASH2_SZ		0x02000000	/* Size of Flash Region 2 */
     57 #define	SI_ARMCM3_ROM		0x1e000000	/* ARM Cortex-M3 ROM */
     58 #define	SI_FLASH1		0x1fc00000	/* MIPS Flash Region 1 */
     59 #define	SI_FLASH1_SZ		0x00400000	/* MIPS Size of Flash Region 1 */
     60 #define	SI_ARM7S_ROM		0x20000000	/* ARM7TDMI-S ROM */
     61 #define	SI_ARMCM3_SRAM2		0x60000000	/* ARM Cortex-M3 SRAM Region 2 */
     62 #define	SI_ARM7S_SRAM2		0x80000000	/* ARM7TDMI-S SRAM Region 2 */
     63 #define	SI_ARM_FLASH1		0xffff0000	/* ARM Flash Region 1 */
     64 #define	SI_ARM_FLASH1_SZ	0x00010000	/* ARM Size of Flash Region 1 */
     65 
     66 #define SI_PCI_DMA		0x40000000	/* Client Mode sb2pcitranslation2 (1 GB) */
     67 #define SI_PCI_DMA2		0x80000000	/* Client Mode sb2pcitranslation2 (1 GB) */
     68 #define SI_PCI_DMA_SZ		0x40000000	/* Client Mode sb2pcitranslation2 size in bytes */
     69 #define SI_PCIE_DMA_L32		0x00000000	/* PCIE Client Mode sb2pcitranslation2
     70 						 * (2 ZettaBytes), low 32 bits
     71 						 */
     72 #define SI_PCIE_DMA_H32		0x80000000	/* PCIE Client Mode sb2pcitranslation2
     73 						 * (2 ZettaBytes), high 32 bits
     74 						 */
     75 
     76 /* core codes */
     77 #define	NODEV_CORE_ID		0x700		/* Invalid coreid */
     78 #define	CC_CORE_ID		0x800		/* chipcommon core */
     79 #define	ILINE20_CORE_ID		0x801		/* iline20 core */
     80 #define	SRAM_CORE_ID		0x802		/* sram core */
     81 #define	SDRAM_CORE_ID		0x803		/* sdram core */
     82 #define	PCI_CORE_ID		0x804		/* pci core */
     83 #define	MIPS_CORE_ID		0x805		/* mips core */
     84 #define	ENET_CORE_ID		0x806		/* enet mac core */
     85 #define	CODEC_CORE_ID		0x807		/* v90 codec core */
     86 #define	USB_CORE_ID		0x808		/* usb 1.1 host/device core */
     87 #define	ADSL_CORE_ID		0x809		/* ADSL core */
     88 #define	ILINE100_CORE_ID	0x80a		/* iline100 core */
     89 #define	IPSEC_CORE_ID		0x80b		/* ipsec core */
     90 #define	UTOPIA_CORE_ID		0x80c		/* utopia core */
     91 #define	PCMCIA_CORE_ID		0x80d		/* pcmcia core */
     92 #define	SOCRAM_CORE_ID		0x80e		/* internal memory core */
     93 #define	MEMC_CORE_ID		0x80f		/* memc sdram core */
     94 #define	OFDM_CORE_ID		0x810		/* OFDM phy core */
     95 #define	EXTIF_CORE_ID		0x811		/* external interface core */
     96 #define	D11_CORE_ID		0x812		/* 802.11 MAC core */
     97 #define	APHY_CORE_ID		0x813		/* 802.11a phy core */
     98 #define	BPHY_CORE_ID		0x814		/* 802.11b phy core */
     99 #define	GPHY_CORE_ID		0x815		/* 802.11g phy core */
    100 #define	MIPS33_CORE_ID		0x816		/* mips3302 core */
    101 #define	USB11H_CORE_ID		0x817		/* usb 1.1 host core */
    102 #define	USB11D_CORE_ID		0x818		/* usb 1.1 device core */
    103 #define	USB20H_CORE_ID		0x819		/* usb 2.0 host core */
    104 #define	USB20D_CORE_ID		0x81a		/* usb 2.0 device core */
    105 #define	SDIOH_CORE_ID		0x81b		/* sdio host core */
    106 #define	ROBO_CORE_ID		0x81c		/* roboswitch core */
    107 #define	ATA100_CORE_ID		0x81d		/* parallel ATA core */
    108 #define	SATAXOR_CORE_ID		0x81e		/* serial ATA & XOR DMA core */
    109 #define	GIGETH_CORE_ID		0x81f		/* gigabit ethernet core */
    110 #define	PCIE_CORE_ID		0x820		/* pci express core */
    111 #define	NPHY_CORE_ID		0x821		/* 802.11n 2x2 phy core */
    112 #define	SRAMC_CORE_ID		0x822		/* SRAM controller core */
    113 #define	MINIMAC_CORE_ID		0x823		/* MINI MAC/phy core */
    114 #define	ARM11_CORE_ID		0x824		/* ARM 1176 core */
    115 #define	ARM7S_CORE_ID		0x825		/* ARM7tdmi-s core */
    116 #define	LPPHY_CORE_ID		0x826		/* 802.11a/b/g phy core */
    117 #define	PMU_CORE_ID		0x827		/* PMU core */
    118 #define	SSNPHY_CORE_ID		0x828		/* 802.11n single-stream phy core */
    119 #define	SDIOD_CORE_ID		0x829		/* SDIO device core */
    120 #define	ARMCM3_CORE_ID		0x82a		/* ARM Cortex M3 core */
    121 #define	QNPHY_CORE_ID		0x82b		/* 802.11n 4x4 phy core */
    122 #define	MIPS74K_CORE_ID		0x82c		/* mips 74k core */
    123 #define	GMAC_CORE_ID		0x82d		/* Gigabit MAC core */
    124 #define	DMEMC_CORE_ID		0x82e		/* DDR1/2 memory controller core */
    125 #define	PCIERC_CORE_ID		0x82f		/* PCIE Root Complex core */
    126 #define	OCP_CORE_ID		0x830		/* OCP2OCP bridge core */
    127 #define	SC_CORE_ID		0x831		/* shared common core */
    128 #define	AHB_CORE_ID		0x832		/* OCP2AHB bridge core */
    129 #define	SPIH_CORE_ID		0x833		/* SPI host core */
    130 #define	I2S_CORE_ID		0x834		/* I2S core */
    131 #define OOB_ROUTER_CORE_ID	0x367		/* OOB router core ID */
    132 #define	DEF_AI_COMP		0xfff		/* Default component, in ai chips it maps all
    133 						 * unused address ranges
    134 						 */
    135 
    136 /* There are TWO constants on all HND chips: SI_ENUM_BASE above,
    137  * and chipcommon being the first core:
    138  */
    139 #define	SI_CC_IDX		0
    140 
    141 /* SOC Interconnect types (aka chip types) */
    142 #define	SOCI_SB			0
    143 #define	SOCI_AI			1
    144 
    145 /* Common core control flags */
    146 #define	SICF_BIST_EN		0x8000
    147 #define	SICF_PME_EN		0x4000
    148 #define	SICF_CORE_BITS		0x3ffc
    149 #define	SICF_FGC		0x0002
    150 #define	SICF_CLOCK_EN		0x0001
    151 
    152 /* Common core status flags */
    153 #define	SISF_BIST_DONE		0x8000
    154 #define	SISF_BIST_ERROR		0x4000
    155 #define	SISF_GATED_CLK		0x2000
    156 #define	SISF_DMA64		0x1000
    157 #define	SISF_CORE_BITS		0x0fff
    158 
    159 /* A register that is common to all cores to
    160  * communicate w/PMU regarding clock control.
    161  */
    162 #define SI_CLK_CTL_ST		0x1e0		/* clock control and status */
    163 
    164 /* clk_ctl_st register */
    165 #define	CCS_FORCEALP		0x00000001	/* force ALP request */
    166 #define	CCS_FORCEHT		0x00000002	/* force HT request */
    167 #define	CCS_FORCEILP		0x00000004	/* force ILP request */
    168 #define	CCS_ALPAREQ		0x00000008	/* ALP Avail Request */
    169 #define	CCS_HTAREQ		0x00000010	/* HT Avail Request */
    170 #define	CCS_FORCEHWREQOFF	0x00000020	/* Force HW Clock Request Off */
    171 #define	CCS_ALPAVAIL		0x00010000	/* ALP is available */
    172 #define	CCS_HTAVAIL		0x00020000	/* HT is available */
    173 #define	CCS0_HTAVAIL		0x00010000	/* HT avail in chipc and pcmcia on 4328a0 */
    174 #define	CCS0_ALPAVAIL		0x00020000	/* ALP avail in chipc and pcmcia on 4328a0 */
    175 
    176 /* Not really related to SOC Interconnect, but a couple of software
    177  * conventions for the use the flash space:
    178  */
    179 
    180 /* Minumum amount of flash we support */
    181 #define FLASH_MIN		0x00020000	/* Minimum flash size */
    182 
    183 /* A boot/binary may have an embedded block that describes its size  */
    184 #define	BISZ_OFFSET		0x3e0		/* At this offset into the binary */
    185 #define	BISZ_MAGIC		0x4249535a	/* Marked with this value: 'BISZ' */
    186 #define	BISZ_MAGIC_IDX		0		/* Word 0: magic */
    187 #define	BISZ_TXTST_IDX		1		/*	1: text start */
    188 #define	BISZ_TXTEND_IDX		2		/*	2: text end */
    189 #define	BISZ_DATAST_IDX		3		/*	3: data start */
    190 #define	BISZ_DATAEND_IDX	4		/*	4: data end */
    191 #define	BISZ_BSSST_IDX		5		/*	5: bss start */
    192 #define	BISZ_BSSEND_IDX		6		/*	6: bss end */
    193 #define BISZ_SIZE		7		/* descriptor size in 32-bit intergers */
    194 
    195 #endif /* _HNDSOC_H */
    196