1 /**************************************************************************** 2 **+-----------------------------------------------------------------------+** 3 **| |** 4 **| Copyright(c) 1998 - 2008 Texas Instruments. All rights reserved. |** 5 **| All rights reserved. |** 6 **| |** 7 **| Redistribution and use in source and binary forms, with or without |** 8 **| modification, are permitted provided that the following conditions |** 9 **| are met: |** 10 **| |** 11 **| * Redistributions of source code must retain the above copyright |** 12 **| notice, this list of conditions and the following disclaimer. |** 13 **| * Redistributions in binary form must reproduce the above copyright |** 14 **| notice, this list of conditions and the following disclaimer in |** 15 **| the documentation and/or other materials provided with the |** 16 **| distribution. |** 17 **| * Neither the name Texas Instruments nor the names of its |** 18 **| contributors may be used to endorse or promote products derived |** 19 **| from this software without specific prior written permission. |** 20 **| |** 21 **| THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |** 22 **| "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |** 23 **| LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |** 24 **| A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |** 25 **| OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |** 26 **| SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |** 27 **| LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |** 28 **| DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |** 29 **| THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |** 30 **| (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |** 31 **| OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |** 32 **| |** 33 **+-----------------------------------------------------------------------+** 34 ****************************************************************************/ 35 36 37 /**************************************************************************** 38 * 39 * MODULE: whalDebug.c 40 * PURPOSE: Handle Debug requests in the Hal 41 * 42 * Register Mac/Phy Read/Write 43 * Register Dump 44 * Register RxDump 45 * Register TxDump 46 * Debug trace print 47 * 48 ****************************************************************************/ 49 #include "whalCommon.h" 50 #include "whalCtrl_api.h" 51 #include "whalCtrl.h" 52 #include "whalSecurity.h" 53 #include "commonTypes.h" 54 #include "CmdQueue_api.h" 55 #include "whalBus_Api.h" 56 #include "TNETW_Driver.h" 57 58 /************************************************ 59 * definitions * 60 ************************************************/ 61 #define BB_REGISTER_ADDR_BASE 0x820000 /*phony address used by host access*/ 62 63 /* 64 * ---------------------------------------------------------------------------- 65 * Function : whalCtrlReadMacReg 66 * 67 * Input : 68 * Output : 69 * Process : 70 * Note(s) : Done 71 * ----------------------------------------------------------------------------- 72 */ 73 UINT32 whalCtrlReadMacReg(TI_HANDLE hWhalCtrl, UINT32 addr) 74 { 75 WHAL_CTRL *pWhalCtrl = (WHAL_CTRL *)hWhalCtrl; 76 77 return whalBus_MacRegRead(pWhalCtrl->pHwCtrl->hWhalBus, addr); 78 } 79 80 /* 81 * ---------------------------------------------------------------------------- 82 * Function : whalCtrlWriteMacReg 83 * 84 * Input : 85 * Output : 86 * Process : 87 * Note(s) : Done 88 * ----------------------------------------------------------------------------- 89 */ 90 void whalCtrlWriteMacReg(TI_HANDLE hWhalCtrl, UINT32 addr, UINT32 val) 91 { 92 WHAL_CTRL *pWhalCtrl = (WHAL_CTRL *)hWhalCtrl; 93 94 whalBus_MacRegWrite(pWhalCtrl->pHwCtrl->hWhalBus, addr, val); 95 } 96 97 /* 98 * ---------------------------------------------------------------------------- 99 * Function : whalCtrlReadPhyReg 100 * 101 * Input : 102 * Output : 103 * Process : 104 * Note(s) : Done 105 * ----------------------------------------------------------------------------- 106 */ 107 UINT32 whalCtrlReadPhyReg(TI_HANDLE hWhalCtrl, UINT32 addr) 108 { 109 WHAL_CTRL *pWhalCtrl = (WHAL_CTRL *)hWhalCtrl; 110 111 return whalBus_PhyRegRead(pWhalCtrl->pHwCtrl->hWhalBus, addr); 112 } 113 114 /* 115 * ---------------------------------------------------------------------------- 116 * Function : whalCtrlWritePhyReg 117 * 118 * Input : 119 * Output : 120 * Process : 121 * Note(s) : Done 122 * ----------------------------------------------------------------------------- 123 */ 124 void whalCtrlWritePhyReg(TI_HANDLE hWhalCtrl, UINT32 addr, UINT32 val) 125 { 126 WHAL_CTRL *pWhalCtrl = (WHAL_CTRL *)hWhalCtrl; 127 128 whalBus_PhyRegWrite(pWhalCtrl->pHwCtrl->hWhalBus, addr, val); 129 } 130 131 132 /* 133 * ---------------------------------------------------------------------------- 134 * Function : whalCtrl_PrintAll 135 * 136 * Input : 137 * Output : 138 * Process : 139 * Note(s) : Done 140 * ----------------------------------------------------------------------------- 141 */ 142 #ifdef TI_DBG 143 void whalCtrl_PrintAll (TI_HANDLE hWhalCtrl) 144 { 145 WHAL_CTRL *pWhalCtrl = (WHAL_CTRL *)hWhalCtrl; 146 147 WLAN_OS_REPORT((" whalCtrl_PrintAll: \n\n")); 148 149 CmdQueue_Print(((TnetwDrv_t*)pWhalCtrl->hTNETW_Driver)->hCmdQueue); 150 151 whalBus_PrintInfo(pWhalCtrl->hWhalBus, BUS_PRINT_ALL, 0); 152 153 whal_hwInfoElemMemoryMapPrint(pWhalCtrl->pHwCtrl->pHwMboxConfig); 154 whal_hwInfoElemStatisticsPrint(pWhalCtrl->pHwCtrl->pHwMboxConfig); 155 156 whal_ParamsHwNvramPrint(pWhalCtrl->pWhalParams); 157 } 158 #endif 159 160 161 /* 162 * ---------------------------------------------------------------------------- 163 * Function : whalCtrl_getMaxNumberOfCommandsInQueue 164 * 165 * Input : 166 * Output : 167 * Process : returns the maximum number of commands in the mailbox queue ever 168 * Note(s) : Done 169 * ----------------------------------------------------------------------------- 170 */ 171 int whalCtrl_getMaxNumberOfCommandsInQueue (TI_HANDLE hWhalCtrl) 172 { 173 WHAL_CTRL *pWhalCtrl = (WHAL_CTRL *)hWhalCtrl; 174 return (CmdQueue_GetMaxNumberOfCommands(((TnetwDrv_t*)pWhalCtrl->hTNETW_Driver)->hCmdQueue)); 175 } 176 177 /* 178 * ---------------------------------------------------------------------------- 179 * Function : whalCtrl_PrintMailBoxHistory 180 * 181 * Input : 182 * Output : 183 * Process : Prints the mailbox command history 184 * Note(s) : Done 185 * ----------------------------------------------------------------------------- 186 */ 187 188 void whalCtrl_PrintMailBoxHistory (TI_HANDLE hWhalCtrl) 189 { 190 #ifdef TI_DBG 191 WHAL_CTRL *pWhalCtrl = (WHAL_CTRL *)hWhalCtrl; 192 CmdQueue_PrintHistory(((TnetwDrv_t*)pWhalCtrl->hTNETW_Driver)->hCmdQueue, 5); 193 #endif 194 } 195 196 /* 197 * ---------------------------------------------------------------------------- 198 * Function : whalCtrl_PrintMem_Regs_CB 199 * 200 * Input : 201 * Output : 202 * Process : 203 * Note(s) : Done 204 * ----------------------------------------------------------------------------- 205 */ 206 void whalCtrl_PrintMem_Regs_CB (TI_HANDLE hWhalCtrl, UINT32 cmdCbStatus) 207 { 208 int i; 209 UINT8 *pBuf; 210 UINT32 result; 211 WHAL_CTRL *pWhalCtrl = (WHAL_CTRL *)hWhalCtrl; 212 213 if (cmdCbStatus != OK) 214 { 215 WLAN_OS_REPORT((" whalCtrl_PrintMem_Regs_CB: command complete error \n\n")); 216 return; 217 } 218 219 result = (((UINT32)pWhalCtrl->printRegsBuf.addr)&0xFFFF0000); 220 221 switch (result) 222 { 223 case ACX_MAC_REG_READ_WRITE_PREFIX: 224 WLAN_OS_REPORT(("MAC REGS (Base=0x%08x) = 0x%08x\n", ((UINT32)pWhalCtrl->printRegsBuf.addr)&0xFFFF, 225 *(UINT32*)(pWhalCtrl->printRegsBuf.value))); 226 break; 227 228 case BB_REGISTER_ADDR_BASE: 229 WLAN_OS_REPORT(("PHY REGS (Base=0x%08x) = 0x%08x\n", ((UINT32)pWhalCtrl->printRegsBuf.addr)&0xFFFF, 230 *(UINT32*)(pWhalCtrl->printRegsBuf.value))); 231 break; 232 233 default: /* Memory*/ 234 for (i=0, pBuf=pWhalCtrl->printRegsBuf.value; i<256; i+=16, pBuf+=16) 235 { 236 WLAN_REPORT_REPLY(pWhalCtrl->hReport, HAL_HW_CTRL_MODULE_LOG, 237 ("PrintBuf: 0x%08x: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x\n", 238 pWhalCtrl->printRegsBuf.addr+i, 239 pBuf[0], pBuf[1], pBuf[2], pBuf[3], pBuf[4], pBuf[5], pBuf[6], pBuf[7], 240 pBuf[8], pBuf[9], pBuf[10], pBuf[11], pBuf[12], pBuf[13], pBuf[14], pBuf[15])); 241 } 242 break; 243 } 244 } 245 246 /* 247 * ---------------------------------------------------------------------------- 248 * Function : whalCtrl_Print_Mem_Regs 249 * 250 * Input : 251 * Output : 252 * Process : 253 * Note(s) : Reading from memory or registers is done through IE (interrogate) 254 * ----------------------------------------------------------------------------- 255 */ 256 void whalCtrl_Print_Mem_Regs (TI_HANDLE hWhalCtrl, UINT32 address, UINT32 len, readWrite_MemoryType_e memType) 257 { 258 ReadWriteCommand_t AcxCmd_ReadMemory; 259 ReadWriteCommand_t* pCmd = &AcxCmd_ReadMemory; 260 261 WHAL_CTRL *pWhalCtrl = (WHAL_CTRL *)hWhalCtrl; 262 263 os_memoryZero(pWhalCtrl->hOs, (void *)pCmd, sizeof(*pCmd)); 264 265 switch (memType) 266 { 267 case TNETW_INTERNAL_RAM: 268 pCmd->addr = (UINT32)ENDIAN_HANDLE_LONG(address); 269 pCmd->size = ENDIAN_HANDLE_LONG(len); 270 break; 271 272 case TNETW_MAC_REGISTERS: 273 pCmd->addr = (UINT32)ENDIAN_HANDLE_LONG(( (address&0xFFFF) | ACX_MAC_REG_READ_WRITE_PREFIX )); 274 pCmd->size = 4; 275 break; 276 277 case TNETW_PHY_REGISTERS: 278 pCmd->addr = (UINT32)ENDIAN_HANDLE_LONG(( (address&0xFFFF) | BB_REGISTER_ADDR_BASE )); 279 pCmd->size = 4; 280 break; 281 282 default: 283 WLAN_OS_REPORT((" whalCtrl_Print_Mem_Regs: ERROR, wrong memory type %d\n\n", memType)); 284 return; 285 } 286 287 os_memoryZero (pWhalCtrl->hOs, (void *)&pWhalCtrl->printRegsBuf, sizeof(pWhalCtrl->printRegsBuf)); 288 289 CmdQueue_CommandWithCb(((TnetwDrv_t*)pWhalCtrl->hTNETW_Driver)->hCmdQueue, CMD_READ_MEMORY, (char *)pCmd, 290 sizeof(*pCmd), (void *)whalCtrl_PrintMem_Regs_CB, hWhalCtrl, 291 &pWhalCtrl->printRegsBuf); 292 } 293 294 295 /* 296 * ---------------------------------------------------------------------------- 297 * Function : whalCtrl_Set_Mem_Regs 298 * 299 * Input : 300 * Output : 301 * Process : 302 * Note(s) : Writing to memory or registers is done through command to the ACX 303 * This function overrides the len parameter and write only 4 bytes! 304 * ----------------------------------------------------------------------------- 305 */ 306 int whalCtrl_Set_Mem_Regs (TI_HANDLE hWhalCtrl, UINT32 address, UINT32 len, UINT32 aWriteVal, 307 readWrite_MemoryType_e memType) 308 { 309 WHAL_CTRL *pWhalCtrl = (WHAL_CTRL *)hWhalCtrl; 310 ReadWriteCommand_t AcxCmd_WriteMemory; 311 ReadWriteCommand_t* pCmd = &AcxCmd_WriteMemory; 312 313 os_memoryZero(pWhalCtrl->hOs, (void *)pCmd, sizeof(*pCmd)); 314 315 switch (memType) 316 { 317 case TNETW_INTERNAL_RAM: 318 pCmd->addr = (UINT32)ENDIAN_HANDLE_LONG(address); 319 pCmd->size = ENDIAN_HANDLE_LONG(len); 320 WLAN_OS_REPORT((" whalCtrl_Set_Mem_Regs: write to Internal Ram addr=0x%x Val=0x%x\n\n", pCmd->addr, aWriteVal)); 321 break; 322 323 case TNETW_MAC_REGISTERS: 324 pCmd->addr = (UINT32)ENDIAN_HANDLE_LONG( (address&0xFFFF) | ACX_MAC_REG_READ_WRITE_PREFIX); 325 pCmd->size = ENDIAN_HANDLE_LONG(len); 326 WLAN_OS_REPORT((" whalCtrl_Set_Mem_Regs: write to Mac register addr=0x%x Val=0x%x\n\n", pCmd->addr, aWriteVal)); 327 break; 328 329 case TNETW_PHY_REGISTERS: 330 pCmd->addr = (UINT32)ENDIAN_HANDLE_LONG( (address&0xFFFF) | BB_REGISTER_ADDR_BASE); 331 pCmd->size = ENDIAN_HANDLE_LONG(len); 332 WLAN_OS_REPORT((" whalCtrl_Set_Mem_Regs: write to Phy register addr=0x%x Val=0x%x\n\n", pCmd->addr, aWriteVal)); 333 break; 334 335 default: 336 WLAN_OS_REPORT((" whalCtrl_Print_Mem_Regs: ERROR, wrong memory type 0x%x\n\n", memType)); 337 return NOK; 338 } 339 340 os_memoryCopy (pWhalCtrl->hOs, (void *)pCmd->value, (void *)&aWriteVal, pCmd->size); 341 342 return (CmdQueue_Command(((TnetwDrv_t*)pWhalCtrl->hTNETW_Driver)->hCmdQueue, CMD_WRITE_MEMORY, (char *)pCmd, sizeof(*pCmd))); 343 } 344 345 346 347
