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    Searched refs:irq_state (Results 1 - 4 of 4) sorted by null

  /external/qemu/hw/
armv7m_nvic.c 172 if (s->gic.irq_state[irq].pending) {
178 if (s->gic.irq_state[ARMV7M_EXCP_SYSTICK].pending)
181 if (s->gic.irq_state[ARMV7M_EXCP_PENDSV].pending)
184 if (s->gic.irq_state[ARMV7M_EXCP_NMI].pending)
207 if (s->gic.irq_state[ARMV7M_EXCP_MEM].active) val |= (1 << 0);
208 if (s->gic.irq_state[ARMV7M_EXCP_BUS].active) val |= (1 << 1);
209 if (s->gic.irq_state[ARMV7M_EXCP_USAGE].active) val |= (1 << 3);
210 if (s->gic.irq_state[ARMV7M_EXCP_SVC].active) val |= (1 << 7);
211 if (s->gic.irq_state[ARMV7M_EXCP_DEBUG].active) val |= (1 << 8);
212 if (s->gic.irq_state[ARMV7M_EXCP_PENDSV].active) val |= (1 << 10)
    [all...]
arm_gic.c 52 #define GIC_SET_ENABLED(irq) s->irq_state[irq].enabled = 1
53 #define GIC_CLEAR_ENABLED(irq) s->irq_state[irq].enabled = 0
54 #define GIC_TEST_ENABLED(irq) s->irq_state[irq].enabled
55 #define GIC_SET_PENDING(irq, cm) s->irq_state[irq].pending |= (cm)
56 #define GIC_CLEAR_PENDING(irq, cm) s->irq_state[irq].pending &= ~(cm)
57 #define GIC_TEST_PENDING(irq, cm) ((s->irq_state[irq].pending & (cm)) != 0)
58 #define GIC_SET_ACTIVE(irq, cm) s->irq_state[irq].active |= (cm)
59 #define GIC_CLEAR_ACTIVE(irq, cm) s->irq_state[irq].active &= ~(cm)
60 #define GIC_TEST_ACTIVE(irq, cm) ((s->irq_state[irq].active & (cm)) != 0)
61 #define GIC_SET_MODEL(irq) s->irq_state[irq].model =
85 gic_irq_state irq_state[GIC_NIRQ]; member in struct:gic_state
    [all...]
pci.c 134 qemu_put_be32(f, s->irq_state[i]);
150 s->irq_state[i] = qemu_get_be32(f);
258 memset(pci_dev->irq_state, 0, sizeof(pci_dev->irq_state));
653 change = level - pci_dev->irq_state[irq_num];
657 pci_dev->irq_state[irq_num] = level;
pci.h 160 int irq_state[4]; member in struct:PCIDevice

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