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  /external/v8/src/mips/
disasm-mips.cc 411 case MTC1:
412 Format(instr, "mtc1 'rt, 'fs");
assembler-mips.h 473 // When paired with MTC1 to write a value to a 64-bit FPR, the MTC1 must be
475 void mtc1(FPURegister fs, Register rt);
assembler-mips.cc 919 void Assembler::mtc1(FPURegister fs, Register rt) { function in class:v8::internal::Assembler
920 GenInstrRegister(COP1, MTC1, rt, fs, f0);

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