| /external/grub/stage2/ |
| hercules.c | 40 outb (unsigned short port, unsigned char value) function
42 asm volatile ("outb %b0, %w1" : : "a" (value), "Nd" (port));
50 outb (HERCULES_INDEX_REG, 0x0f);
51 outb (0x80, 0);
52 outb (HERCULES_DATA_REG, offset & 0xFF);
53 outb (0x80, 0);
55 outb (HERCULES_INDEX_REG, 0x0e);
56 outb (0x80, 0);
57 outb (HERCULES_DATA_REG, offset >> 8);
58 outb (0x80, 0)
[all...] |
| serial.c | 71 asm volatile ("outb %%al, $0x80" : : );
78 outb (unsigned short port, unsigned char value)
80 asm volatile ("outb %b0, %w1" : : "a" (value), "Nd" (port));
81 asm volatile ("outb %%al, $0x80" : : );
108 outb (serial_hw_port + UART_TX, c);
114 outb (0x80, 0);
143 outb (port + UART_IER, 0);
146 outb (port + UART_LCR, UART_DLAB);
159 outb (port + UART_DLL, div & 0xFF);
160 outb (port + UART_DLH, div >> 8)
77 outb (unsigned short port, unsigned char value) function
[all...] |
| smp-imps.c | 82 outb (unsigned short port, unsigned char val) function
84 __asm __volatile ("outb %0,%1"::"a" (val), "d" (port));
91 outb (0x70, loc);
92 outb (0x71, val);
98 outb (0x70, loc);
|
| /external/grub/netboot/ |
| timer.c | 16 outb((inb(PPC_PORTB) & ~PPCB_SPKR) | PPCB_T2GATE, PPC_PORTB);
17 outb(TIMER2_SEL|WORD_ACCESS|MODE0|BINARY_COUNT, TIMER_MODE_PORT);
18 outb(ticks & 0xFF, TIMER2_PORT);
19 outb(ticks >> 8, TIMER2_PORT);
50 outb((inb(0x61) & ~0x02) | 0x01, 0x61);
59 outb(0xb0, 0x43); /* binary, mode 0, LSB/MSB, Ch 2 */
60 outb(CALIBRATE_LATCH & 0xff, 0x42); /* LSB of count */
61 outb(CALIBRATE_LATCH >> 8, 0x42); /* MSB of count */
|
| ns8390.c | 111 outb(D8390_COMMAND_RD2 |
113 outb(cnt, eth_nic_base + D8390_P0_RBCR0);
114 outb(cnt>>8, eth_nic_base + D8390_P0_RBCR1);
115 outb(src, eth_nic_base + D8390_P0_RSAR0);
116 outb(src>>8, eth_nic_base + D8390_P0_RSAR1);
117 outb(D8390_COMMAND_RD0 |
121 outb(src & 0xff, eth_asic_base + _3COM_DALSB);
122 outb(src >> 8, eth_asic_base + _3COM_DAMSB);
123 outb(t503_output | _3COM_CR_START, eth_asic_base + _3COM_CR);
144 outb(t503_output, eth_asic_base + _3COM_CR)
[all...] |
| ni5010.c | 188 outb(RS_VALID_BITS, EDLC_RCLR); /* Clear all pending Rcv interrupts */
189 outb(MM_EN_RCV, IE_MMODE); /* Enable rcv */
200 outb(RS_RESET, EDLC_RESET); /* Hold up EDLC_RESET while configing board */
201 outb(0, IE_RESET); /* Hardware reset of ni5010 board */
202 outb(0, EDLC_XMASK); /* Disable all Xmt interrupts */
203 outb(0, EDLC_RMASK); /* Disable all Rcv interrupt */
204 outb(0xFF, EDLC_XCLR); /* Clear all pending Xmt interrupts */
205 outb(0xFF, EDLC_RCLR); /* Clear all pending Rcv interrupts */
206 outb(XMD_LBC, EDLC_XMODE); /* Only loopback xmits */
209 outb(nic->node_addr[i], EDLC_ADDR + i)
[all...] |
| tiara.c | 118 outb(CARD_DISABLE, ioaddr + DLCR_ENABLE);
119 outb(CLEAR_STATUS, ioaddr + DLCR_XMIT_STAT);
120 outb(NO_TX_IRQS, ioaddr + DLCR_XMIT_MASK);
121 outb(CLR_RCV_STATUS, ioaddr + DLCR_RECV_STAT);
122 outb(XMIT_MODE, ioaddr + DLCR_XMIT_MODE);
123 outb(RECV_MODE, ioaddr + DLCR_RECV_MODE);
129 outb(nic->node_addr[i], ioaddr + DLCR_NODE_ID + i);
130 outb(CLR_RCV_STATUS, ioaddr + DLCR_RECV_STAT);
131 outb(CARD_ENABLE, ioaddr + DLCR_ENABLE);
180 outb(p[s-1], ioaddr + BMPR_MEM_PORT)
[all...] |
| eepro.c | 261 #define eepro_full_reset(ioaddr) outb(RESET_CMD, ioaddr); udelay(40);
265 outb(SEL_RESET_CMD, ioaddr); \
271 #define eepro_clear_int(ioaddr) outb(ALL_MASK, ioaddr + STATUS_REG)
274 #define eepro_en_rx(ioaddr) outb(RCV_ENABLE_CMD, ioaddr)
277 #define eepro_dis_rx(ioaddr) outb(RCV_DISABLE_CMD, ioaddr)
280 #define eepro_sw2bank0(ioaddr) outb(BANK0_SELECT, ioaddr)
281 #define eepro_sw2bank1(ioaddr) outb(BANK1_SELECT, ioaddr)
282 #define eepro_sw2bank2(ioaddr) outb(BANK2_SELECT, ioaddr)
307 outb(temp_reg & 0xEF, ioaddr + eeprom_reg);
309 outb(nic->node_addr[i], ioaddr + I_ADD_REG0 + i)
[all...] |
| rtl8139.c | 200 outb(0x00, ioaddr + Config1);
258 outb(EE_ENB & ~EE_CS, ee_addr);
259 outb(EE_ENB, ee_addr);
264 outb(EE_ENB | dataval, ee_addr);
266 outb(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
269 outb(EE_ENB, ee_addr);
273 outb(EE_ENB | EE_SHIFT_CLK, ee_addr);
276 outb(EE_ENB, ee_addr);
281 outb(~EE_CS, ee_addr);
289 outb(CmdReset, ioaddr + ChipCmd)
[all...] |
| 3c509.c | 107 outb(nic->node_addr[i], BASE + EP_W2_ADDR_0 + i);
190 outb(0x0, BASE + EP_W1_TX_STATUS);
205 outb(*(p+s - 1), BASE + EP_W1_TX_PIO_WR_1);
208 outb(0, BASE + EP_W1_TX_PIO_WR_1); /* Padding */
341 outb(al, port);
366 outb(0x80 + offset, id_port);
376 outb(0xc0, EP_ID_PORT);
477 outb(W0_P4_CMD_RESET_ADAPTER, io_base + EP_W0_CONFIG_CTRL);
479 outb(W0_P4_CMD_ENABLE_ADAPTER, io_base + EP_W0_CONFIG_CTRL);
492 outb(0xc0, id_port); /* Global reset *
[all...] |
| via-rhine.c | 751 outb (byMIICRbak & 0x7f, byMIICR);
754 outb (byMIIIndex, byMIIAD);
757 outb (inb (byMIICR) | 0x40, byMIICR);
771 outb (byMIIAdrbak, byMIIAD);
772 outb (byMIICRbak, byMIICR);
792 outb (byMIICRbak & 0x7f, byMIICR);
794 outb (byMIISetByte, byMIIAD);
797 outb (inb (byMIICR) | 0x40, byMIICR);
827 outb (inb (byMIICR) | 0x20, byMIICR);
838 outb (byMIIAdrbak & 0x7f, byMIIAD)
[all...] |
| i82586.c | 311 outb(0, ioaddr + I82586_ATTN);
328 outb(0x20, ioaddr + MISC_CTRL);
345 outb(0xA0, ioaddr + MISC_CTRL);
350 outb(0, ioaddr + I82586_ATTN);
363 outb(0, ioaddr + I82586_ATTN);
367 outb(0x80, ioaddr + MISC_CTRL);
488 outb(0, ioaddr + I82586_ATTN);
490 outb(0, ioaddr + NI52_RESET);
524 outb(0x01, ioaddr + MISC_CTRL);
549 outb(0x00, ID_PORT)
[all...] |
| 3c595.c | 109 outb(nic->node_addr[i], BASE + VX_W2_ADDR_0 + i);
199 outb(0x0, BASE + VX_W1_TX_STATUS);
215 outb(*(p+s - 1), BASE + VX_W1_TX_PIO_WR_1);
218 outb(0, BASE + VX_W1_TX_PIO_WR_1); /* Padding */
|
| sis900.c | 199 outb(0x09 + i, 0x70);
363 outb(EECS, ee_addr);
456 outb(dataval, mdio_addr);
458 outb(dataval | MDC, mdio_addr);
475 outb(0, mdio_addr);
477 outb(MDC, mdio_addr);
|
| cs89x0.c | 319 outb(eth_irq, eth_nic_base + DATA_PORT);
320 outb(0, eth_nic_base + DATA_PORT + 1); }
324 outb((eth_mem_start >> 8) & 0xff, eth_nic_base + DATA_PORT);
325 outb((eth_mem_start >> 24) & 0xff, eth_nic_base + DATA_PORT + 1); } }
|
| depca.c | 544 outb(nicsr, DEPCA_NICSR);
678 outb(nicsr, DEPCA_NICSR);
692 outb(nicsr, DEPCA_NICSR);
719 outb(nicsr |= SHE, DEPCA_NICSR);
|
| /prebuilt/linux-x86/toolchain/i686-unknown-linux-gnu-4.2.1/lib/gcc/i686-unknown-linux-gnu/4.2.1/include/xorg/ |
| compiler.h | 95 # define outb RealOutb macro
104 # define outb outp macro
139 extern void outb(unsigned short, unsigned char);
148 extern void outb(unsigned long, unsigned char);
184 outb(unsigned long port, unsigned char val) function
234 extern void outb(unsigned int port, unsigned char val);
504 # undef outb macro
510 extern void outb(unsigned long port, unsigned char val);
535 outb(unsigned short port, unsigned char val) function
537 __asm__ __volatile__("outb %0,%1" : :"a" (val), "d" (port))
593 outb(unsigned long port, unsigned char val) function
927 outb(unsigned PORT_SIZE port, unsigned char val) function
1258 outb(unsigned short port, unsigned char value) function
1353 #define outb macro
1388 outb(unsigned short port, unsigned char val) function
1439 outb(unsigned short port, unsigned char val) function
1491 outb(unsigned short port, unsigned char val) function
1566 # undef outb macro
1579 # define outb macro
1594 # define outb macro
1670 # undef outb macro
1677 # define outb macro
[all...] |
| /bionic/libc/kernel/arch-x86/asm/ |
| dma_32.h | 22 #define dma_outb outb
|
| /bionic/libm/i387/ |
| npx.h | 147 #define npx_full_reset() outb(IO_NPX + 1, 0)
|
| /ndk/build/platforms/android-5/arch-x86/usr/include/asm/ |
| dma_32.h | 22 #define dma_outb outb
|
| /ndk/build/platforms/android-8/arch-x86/usr/include/asm/ |
| dma_32.h | 22 #define dma_outb outb
|
| /external/quake/quake/src/QW/client/ |
| d_copy.s | 42 outb %al,%dx // point the SC to the Map Mask
65 outb %al,%dx
|
| vid_svgalib.c | 130 outb(0x02, 0x3C4);
131 outb(1 << plane, 0x3C5);
132 outb(4, 0x3CE);
133 outb(plane, 0x3CF);
194 outb(2, 0x3C4);
195 outb(1 << plane, 0x3C5);
196 outb(4, 0x3CE);
197 outb(plane, 0x3CF);
|
| /external/quake/quake/src/WinQuake/ |
| d_copy.s | 42 outb %al,%dx // point the SC to the Map Mask
65 outb %al,%dx
|
| vid_svgalib.cpp | 129 outb(0x02, 0x3C4);
130 outb(1 << plane, 0x3C5);
131 outb(4, 0x3CE);
132 outb(plane, 0x3CF);
193 outb(2, 0x3C4);
194 outb(1 << plane, 0x3C5);
195 outb(4, 0x3CE);
196 outb(plane, 0x3CF);
|
