| /dalvik/vm/mterp/out/ |
| InterpAsm-armv5te-vfp.S | 140 * We want to write "ldrh rINST, [rPC, _reg, lsl #2]!", but some of the
177 #define GOTO_OPCODE(_reg) add pc, rIBASE, _reg, lsl #6
178 #define GOTO_OPCODE_IFEQ(_reg) addeq pc, rIBASE, _reg, lsl #6
179 #define GOTO_OPCODE_IFNE(_reg) addne pc, rIBASE, _reg, lsl #6
184 #define GET_VREG(_reg, _vreg) ldr _reg, [rFP, _vreg, lsl #2]
185 #define SET_VREG(_reg, _vreg) str _reg, [rFP, _vreg, lsl #2]
196 add _reg, rFP, _vreg, lsl #2
479 add r3, rFP, r3, lsl #2 @ r3<- &fp[B]
480 add r2, rFP, r2, lsl #2 @ r2<- &fp[A]
496 add r3, rFP, r3, lsl #2 @ r3<- &fp[BBBB
[all...] |
| InterpAsm-armv7-a-neon.S | 140 * We want to write "ldrh rINST, [rPC, _reg, lsl #2]!", but some of the
177 #define GOTO_OPCODE(_reg) add pc, rIBASE, _reg, lsl #6
178 #define GOTO_OPCODE_IFEQ(_reg) addeq pc, rIBASE, _reg, lsl #6
179 #define GOTO_OPCODE_IFNE(_reg) addne pc, rIBASE, _reg, lsl #6
184 #define GET_VREG(_reg, _vreg) ldr _reg, [rFP, _vreg, lsl #2]
185 #define SET_VREG(_reg, _vreg) str _reg, [rFP, _vreg, lsl #2]
196 add _reg, rFP, _vreg, lsl #2
477 add r3, rFP, r3, lsl #2 @ r3<- &fp[B]
478 add r2, rFP, r2, lsl #2 @ r2<- &fp[A]
494 add r3, rFP, r3, lsl #2 @ r3<- &fp[BBBB
[all...] |
| InterpAsm-armv7-a.S | 140 * We want to write "ldrh rINST, [rPC, _reg, lsl #2]!", but some of the
177 #define GOTO_OPCODE(_reg) add pc, rIBASE, _reg, lsl #6
178 #define GOTO_OPCODE_IFEQ(_reg) addeq pc, rIBASE, _reg, lsl #6
179 #define GOTO_OPCODE_IFNE(_reg) addne pc, rIBASE, _reg, lsl #6
184 #define GET_VREG(_reg, _vreg) ldr _reg, [rFP, _vreg, lsl #2]
185 #define SET_VREG(_reg, _vreg) str _reg, [rFP, _vreg, lsl #2]
196 add _reg, rFP, _vreg, lsl #2
477 add r3, rFP, r3, lsl #2 @ r3<- &fp[B]
478 add r2, rFP, r2, lsl #2 @ r2<- &fp[A]
494 add r3, rFP, r3, lsl #2 @ r3<- &fp[BBBB
[all...] |
| /system/core/include/private/pixelflinger/ |
| ggl_fixed.h | 116 "adc %[lo], %[lo], %[hi], lsl %[lshift] \n"
124 "adc %[lo], %[lo], %[hi], lsl %[lshift] \n"
139 "add %[lo], %[lo], %[hi], lsl %[lshift] \n"
146 "add %[lo], %[lo], %[hi], lsl %[lshift] \n"
160 "add %[lo], %[lo], %[hi], lsl %[lshift] \n"
167 "add %[lo], %[lo], %[hi], lsl %[lshift] \n"
|
| /dalvik/vm/compiler/codegen/arm/ |
| ArmLIR.h | 378 kThumbLslRRI5, /* lsl(1) [00000] imm_5[10..6] rm[5..3] rd[2..0] */
379 kThumbLslRR, /* lsl(2) [0100000010] rs[5..3] rd[2..0] */
493 kThumb2LdrRRR, /* ldr rt,[rn,rm,LSL #imm] [111110000101] rn[19-16]
495 kThumb2LdrhRRR, /* ldrh rt,[rn,rm,LSL #imm] [111110000101] rn[19-16]
497 kThumb2LdrshRRR, /* ldrsh rt,[rn,rm,LSL #imm] [111110000101] rn[19-16]
499 kThumb2LdrbRRR, /* ldrb rt,[rn,rm,LSL #imm] [111110000101] rn[19-16]
501 kThumb2LdrsbRRR, /* ldrsb rt,[rn,rm,LSL #imm] [111110000101] rn[19-16]
503 kThumb2StrRRR, /* str rt,[rn,rm,LSL #imm] [111110000100] rn[19-16]
505 kThumb2StrhRRR, /* str rt,[rn,rm,LSL #imm] [111110000010] rn[19-16]
507 kThumb2StrbRRR, /* str rt,[rn,rm,LSL #imm] [111110000000] rn[19-16
[all...] |
| /dalvik/vm/mterp/armv5te/ |
| OP_NEW_ARRAY.S | 18 ldr r0, [r3, r2, lsl #2] @ r0<- resolved class
|
| OP_NEW_INSTANCE.S | 16 ldr r0, [r3, r1, lsl #2] @ r0<- resolved class
|
| OP_CHECK_CAST.S | 19 ldr r1, [r0, r2, lsl #2] @ r1<- resolved class
|
| OP_INSTANCE_OF.S | 24 ldr r1, [r2, r3, lsl #2] @ r1<- resolved class
|
| /external/opencore/codecs_v2/audio/gsm_amr/amr_wb/dec/src/ |
| pvamrwbdecoder_basic_op_gcc_armv5.h | 67 "mov %0, %2, lsl #16\n"
68 "mov %1, %3, lsl #16\n"
88 "mov %0, %2, lsl #16\n"
89 "mov %1, %3, lsl #16\n"
|
| /external/openssl/crypto/0.9.9-dev/sha/ |
| sha256-armv4.pl | 48 orr $T1,$T1,$t2,lsl#8
49 orr $T1,$T1,$t1,lsl#16
50 orr $T1,$T1,$t0,lsl#24
129 add $len,$inp,$len,lsl#6 @ len to point at the end of inp
|
| sha1-armv4-large.pl | 68 orr $t0,$t1,$t0,lsl#8
70 orr $t0,$t2,$t0,lsl#8
72 orr $t0,$t1,$t0,lsl#8
151 add $len,$inp,$len,lsl#6 @ $len to point at the end of $inp
|
| /frameworks/base/media/libstagefright/codecs/amrwb/src/ |
| pvamrwbdecoder_basic_op_gcc_armv5.h | 67 "mov %0, %2, lsl #16\n"
68 "mov %1, %3, lsl #16\n"
88 "mov %0, %2, lsl #16\n"
89 "mov %1, %3, lsl #16\n"
|
| /sdk/emulator/qtools/ |
| opcode.cpp | 184 "lsl",
|
| /external/sonivox/arm-hybrid-22k/lib_src/ |
| ARM-E_voice_gain_gnu.s | 138 MOV gain, gain, LSL #(NUM_MIXER_GUARD_BITS + 4)
140 MOV gainIncrement, gainIncrement, LSL #(NUM_MIXER_GUARD_BITS + 4)
|
| ARM-E_interpolate_loop_gnu.s | 105 MOV tmp0, tmp0, LSL #6 @ boost 8-bit signal by 36dB
|
| /external/sonivox/arm-wt-22k/lib_src/ |
| ARM-E_voice_gain_gnu.s | 138 MOV gain, gain, LSL #(NUM_MIXER_GUARD_BITS + 4)
140 MOV gainIncrement, gainIncrement, LSL #(NUM_MIXER_GUARD_BITS + 4)
|
| ARM-E_interpolate_loop_gnu.s | 105 MOV tmp0, tmp0, LSL #6 @ boost 8-bit signal by 36dB
|
| /external/speex/libspeex/ |
| fixed_arm4.h | 45 "add %0, %0, %1, lsl #18 \n\t"
58 "add %0, %0, %1, lsl #17 \n\t"
|
| /external/opencore/codecs_v2/video/avc_h264/enc/src/ |
| sad_inline.h | 195 RSB x7, x7, x7, lsl #8; local
213 RSB x7, x7, x7, lsl #8; local
261 MOVS x8, ref, lsl #31 ; local
351 __asm__ volatile("EOR %1, %2, %0\n\tSUBS %0, %2, %0\n\tEOR %1, %1, %0\n\tAND %1, %3, %1, lsr #1\n\tORRCC %1, %1, #0x80000000\n\tRSB %1, %1, %1, lsl #8\n\tADD %0, %0, %1, asr #7\n\tEOR %0, %0, %1, asr #7": "=r"(src1), "=&r"(x7): "r"(src2), "r"(mask));
360 __asm__ volatile("EOR %1, %2, %0\n\tADDS %0, %2, %0\n\tEOR %1, %1, %0\n\tANDS %1, %3, %1, rrx\n\tRSB %1, %1, %1, lsl #8\n\tSUB %0, %0, %1, asr #7\n\tEOR %0, %0, %1, asr #7": "=r"(src1), "=&r"(x7): "r"(src2), "r"(mask));
|
| /external/opencore/codecs_v2/video/m4v_h263/enc/src/ |
| sad_inline.h | 200 RSB x7, x7, x7, lsl #8; local
218 RSB x7, x7, x7, lsl #8; local
266 MOVS x8, ref, lsl #31 ; local
378 "rsb %0, %0, %0, lsl #8\n\t"
402 "rsb %1, %1, %1, lsl #8\n\t"
|
| /system/core/libpixelflinger/codeflinger/ |
| texturing.cpp | 531 MOV(GE, 0, width, reg_imm(width, LSL, shift));
548 MOV(LE, 0, u, reg_imm(width, LSL, FRAC_BITS));
566 MOV(GE, 0, height, reg_imm(height, LSL, shift));
572 MOV(LE, 0, v, reg_imm(height, LSL, FRAC_BITS));
575 MOV(GT, 0, height, reg_imm(stride, LSL, shift));
814 ORR(AL, 0, pixel, pixel, reg_imm(pixel, LSL, shift));
829 ORR(AL, 0, pixel, pixel, reg_imm(pixel, LSL, shift));
843 ORR(AL, 0, pixel, pixel, reg_imm(pixel, LSL, shift));
856 ORR(AL, 0, pixel, pixel, reg_imm(pixel, LSL, shift));
[all...] |
| /dalvik/vm/compiler/template/armv5te/ |
| TEMPLATE_INVOKE_METHOD_NATIVE.S | 7 sub r1, r1, r7, lsl #2 @ r1<- newFp (old savearea - regsSize)
|
| /external/tremolo/Tremolo/ |
| floor1LARM.s | 54 LDR r5, [r2], r3,LSL #2 @ r5 = *floor r2 = floor+base
|
| /external/v8/src/arm/ |
| assembler-arm-inl.h | 187 shift_op_ = LSL;
195 shift_op_ == LSL &&
|
