| /dalvik/vm/mterp/armv4t/ |
| OP_IPUT_WIDE.S | 12 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
34 add r2, rFP, r2, lsl #2 @ r3<- &fp[A]
|
| OP_SPUT_WIDE.S | 13 ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr
14 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
|
| /dalvik/vm/mterp/armv5te/ |
| OP_IGET_WIDE.S | 15 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
40 add r3, rFP, r2, lsl #2 @ r3<- &fp[A]
|
| OP_INVOKE_VIRTUAL.S | 16 ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod
44 ldr r0, [r3, r2, lsl #2] @ r3<- vtable[methodIndex]
|
| OP_IPUT_WIDE.S | 12 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
34 add r2, rFP, r2, lsl #2 @ r3<- &fp[A]
|
| OP_SHL_LONG.S | 13 add r3, rFP, r3, lsl #2 @ r3<- &fp[BB]
17 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
|
| OP_SHR_LONG.S | 13 add r3, rFP, r3, lsl #2 @ r3<- &fp[BB]
17 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
|
| OP_USHR_LONG.S | 13 add r3, rFP, r3, lsl #2 @ r3<- &fp[BB]
17 add r9, rFP, r9, lsl #2 @ r9<- &fp[AA]
|
| binopWide2addr.S | 20 add r1, rFP, r1, lsl #2 @ r1<- &fp[B]
21 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
|
| header.S | 133 * We want to write "ldrh rINST, [rPC, _reg, lsl #2]!", but some of the
170 #define GOTO_OPCODE(_reg) add pc, rIBASE, _reg, lsl #${handler_size_bits}
171 #define GOTO_OPCODE_IFEQ(_reg) addeq pc, rIBASE, _reg, lsl #${handler_size_bits}
172 #define GOTO_OPCODE_IFNE(_reg) addne pc, rIBASE, _reg, lsl #${handler_size_bits}
177 #define GET_VREG(_reg, _vreg) ldr _reg, [rFP, _vreg, lsl #2]
178 #define SET_VREG(_reg, _vreg) str _reg, [rFP, _vreg, lsl #2]
189 add _reg, rFP, _vreg, lsl #2
|
| /dalvik/vm/mterp/armv6t2/ |
| OP_IGET_WIDE.S | 15 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
39 add r3, rFP, r2, lsl #2 @ r3<- &fp[A]
|
| OP_IPUT_WIDE.S | 12 ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr
33 add r2, rFP, r2, lsl #2 @ r3<- &fp[A]
|
| binopWide2addr.S | 19 add r1, rFP, r1, lsl #2 @ r1<- &fp[B]
20 add r9, rFP, r9, lsl #2 @ r9<- &fp[A]
|
| /external/opencore/codecs_v2/audio/mp3/dec/src/asm/ |
| pvmp3_dct_9_arm.s | 83 mov r9,r1,lsl #1
102 mov r1,r12,lsl #1
120 mov r1,r6,lsl #1
129 mov r1,r5,lsl #1
135 mov r2,r4,lsl #1
139 mov r3,r3,lsl #1
145 mov r12,lr,lsl #1
151 mov lr,lr,lsl #1
|
| pvmp3_dct_9_gcc.s | 73 mov r9,r1,lsl #1
86 mov r1,r12,lsl #1
109 mov r1,r6,lsl #1
118 mov r1,r5,lsl #1
124 mov r2,r4,lsl #1
128 mov r3,r3,lsl #1
134 mov r12,lr,lsl #1
140 mov lr,lr,lsl #1
|
| pvmp3_polyphase_filter_window_arm.s | 66 add r3,r0,r2,lsl #2
70 add r12,r0,r2,lsl #2
158 mov r2,r10,lsl r2
159 add r4,r4,r2,lsl #1
168 rsb r2,r2,r12,lsl #5
169 add r2,r11,r2,lsl #1
182 add r2,r0,r3,lsl #2
222 mov r1,r1,lsl r2
223 add r1,r12,r1,lsl #1
|
| /frameworks/base/media/libstagefright/codecs/mp3dec/src/asm/ |
| pvmp3_dct_9_arm.s | 83 mov r9,r1,lsl #1
102 mov r1,r12,lsl #1
120 mov r1,r6,lsl #1
129 mov r1,r5,lsl #1
135 mov r2,r4,lsl #1
139 mov r3,r3,lsl #1
145 mov r12,lr,lsl #1
151 mov lr,lr,lsl #1
|
| pvmp3_dct_9_gcc.s | 73 mov r9,r1,lsl #1
86 mov r1,r12,lsl #1
109 mov r1,r6,lsl #1
118 mov r1,r5,lsl #1
124 mov r2,r4,lsl #1
128 mov r3,r3,lsl #1
134 mov r12,lr,lsl #1
140 mov lr,lr,lsl #1
|
| pvmp3_polyphase_filter_window_arm.s | 66 add r3,r0,r2,lsl #2
70 add r12,r0,r2,lsl #2
158 mov r2,r10,lsl r2
159 add r4,r4,r2,lsl #1
168 rsb r2,r2,r12,lsl #5
169 add r2,r11,r2,lsl #1
182 add r2,r0,r3,lsl #2
222 mov r1,r1,lsl r2
223 add r1,r12,r1,lsl #1
|
| /system/core/libpixelflinger/codeflinger/ |
| load_store.cpp | 81 ORR(AL, 0, s.reg, s.reg, reg_imm(s0, LSL, 8));
83 ORR(AL, 0, s.reg, s.reg, reg_imm(s0, LSL, 16));
88 ORR(AL, 0, s1, s1, reg_imm(s0, LSL, 8));
90 ORR(AL, 0, s.reg, s1, reg_imm(s0, LSL, 16));
120 MOV(AL, 0, d.reg, reg_imm(s, LSL, 32-h));
195 RSB(AL, 0, d, s, reg_imm(s, LSL, dbits));
201 MOV(AL, 0, d, reg_imm(s, LSL, dbits-sbits));
215 ORR(AL, 0, d, s, reg_imm(s, LSL, sbits));
293 MOV(AL, 0, ireg, reg_imm(s.reg, LSL, 32-sh));
331 else if (shift<0) ADD(AL, 0, ireg, ireg, reg_imm(dither.reg, LSL,-shift))
[all...] |
| /bionic/libc/arch-arm/bionic/ |
| memcmp.S | 206 orr ip, ip, lr, lsl #16
211 orreq ip, ip, lr, lsl #16
216 orreq ip, ip, lr, lsl #16
221 orreq ip, ip, lr, lsl #16
249 mov r5, r0, lsl #3 /* r5 = right shift */
260 orr ip, ip, r7, lsl r6
265 orreq ip, ip, r7, lsl r6
|
| ffs.S | 56 orrne r0, r0, r0, lsl #4 /* r0 = X * 0x11 */
57 orrne r0, r0, r0, lsl #6 /* r0 = X * 0x451 */
58 rsbne r0, r0, r0, lsl #16 /* r0 = X * 0x0450fbaf */
|
| /external/opencore/codecs_v2/video/m4v_h263/enc/src/ |
| sad_mb_offset.h | 84 x10 = x10 | (x11 << (32 - SHIFT)); /* bic x10, x10, x11, lsl #8 = ~G ~F ~E ~D */
162 BIC x10, x10, x11, lsl #(32-SHIFT);
164 BIC x11, x11, x12, lsl #(32-SHIFT);
185 BIC x10, x10, x11, lsl #(32-SHIFT);
187 BIC x11, x11, x12, lsl #(32-SHIFT);
256 "bic %0, %0, %1, lsl %6\n\t"
258 "bic %1, %1, %2, lsl %6\n\t"
278 "bic %0, %0, %1, lsl %6\n\t"
280 "bic %1, %1, %2, lsl %6\n\t"
|
| /system/core/libpixelflinger/ |
| t32cb16blend.S | 63 orrlo \FB, \FB, lr, lsl #(16 + 11)
73 orrlo \FB, \FB, r6, lsl #(16 + 5)
83 orrlo \FB, \FB, lr, lsl #16
96 movlo \FB, lr, lsl #11
107 orrlo \FB, \FB, r6, lsl #5
|
| /dalvik/vm/compiler/template/armv5te/ |
| TEMPLATE_INVOKE_METHOD_CHAIN.S | 15 sub r1, r1, r7, lsl #2 @ r1<- newFp (old savearea - regsSize)
18 sub r10, r10, r2, lsl #2 @ r10<- bottom (newsave - outsSize)
|
