| /external/webkit/LayoutTests/http/tests/appcache/ |
| top-frame-1-expected.txt | 3 Techically, the check is that iframe subresources that are not in top frame cache are loaded anyway, so it can also pass if the UA fails to reject loads for cache misses.
|
| top-frame-1.html | 6 anyway, so it can also pass if the UA fails to reject loads for cache misses.</p>
|
| /frameworks/base/core/tests/coretests/src/android/widget/listview/ |
| ListHeterogeneousTest.java | 64 assertEquals("Unexpected convert misses", 0, convertMissesBefore);
72 assertEquals("Unexpected convert misses", 0, convertMissesAfter);
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| /prebuilt/linux-x86/oprofile/arm/armv6/ |
| events | 3 event:0x00 counters:0,1 um:zero minimum:500 name:IFU_IFETCH_MISS : number of instruction fetch misses
6 event:0x03 counters:0,1 um:zero minimum:500 name:ITLB_MISS : number of Instruction MicroTLB misses
7 event:0x04 counters:0,1 um:zero minimum:500 name:DTLB_MISS : number of Data MicroTLB misses
|
| /prebuilt/linux-x86_64/oprofile/arm/armv6/ |
| events | 3 event:0x00 counters:0,1 um:zero minimum:500 name:IFU_IFETCH_MISS : number of instruction fetch misses
6 event:0x03 counters:0,1 um:zero minimum:500 name:ITLB_MISS : number of Instruction MicroTLB misses
7 event:0x04 counters:0,1 um:zero minimum:500 name:DTLB_MISS : number of Data MicroTLB misses
|
| /external/bluetooth/glib/gio/inotify/ |
| inotify-kernel.h | 51 guint32 *misses);
|
| inotify-kernel.c | 324 guint32 *misses)
329 if (misses)
330 *misses = ik_move_misses;
|
| /external/icu4c/i18n/ |
| csr2022.cpp | 37 int32_t misses = 0; local
68 misses += 1;
89 quality = (100*hits - 100*misses) / (hits + misses);
|
| /external/iproute2/doc/ |
| rtstat.sgml | 18 in a vmstat or iostat manner. The ratio between cache hits and misses gives
|
| /hardware/broadcom/wlan/bcm4329/src/include/ |
| bcmperf.h | 29 /* get cache hits and misses */
|
| /external/qemu/ |
| dcache.c | 124 uint64_t misses = dcache.load_misses + dcache.store_misses; local
125 uint64_t total = hits + misses;
130 miss_per = 100.0 * misses / total;
134 printf("Dcache misses %10llu %6.2f%%\n", misses, miss_per);
135 printf("Dcache total %10llu\n", hits + misses);
|
| /external/bzip2/ |
| mk251.c | 4 1007 in blocksort.c. This assertion misses an extremely rare
|
| /external/kernel-headers/original/asm-arm/ |
| domain.h | 26 * supersections to reduce TLB misses and footprint.
|
| /dalvik/vm/ |
| AtomicCache.c | 128 pCache->misses++;
167 pCache->misses, pCache->fills,
170 (pCache->fail + pCache->hits + pCache->misses + pCache->fills),
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| AtomicCache.h | 58 int misses; /* entry was for other keys */ member in struct:AtomicCache
|
| /dalvik/libcore/x-net/src/main/java/org/apache/harmony/xnet/provider/jsse/ |
| FileClientSessionCache.java | 53 * cache hits, but not on cache misses.
94 // cache misses in getSessionData().
133 * in SSLSessionContext misses, so it would be unnecesarily
|
| /external/oprofile/opcontrol/ |
| opcontrol.cpp | 90 "number of instruction fetch misses"},
96 "number of Instruction MicroTLB misses"},
98 "number of Data MicroTLB misses"},
130 "Instruction fetch misses from cache or normal cacheable memory"},
132 "Instruction fetch misses from TLB"},
|
| /external/qemu/slirp/ |
| debug.c | 167 lprint(" %6d searches for connection stats (%d misses)\r\n",
236 lprint(" %6d TCP cache misses\r\n", tcpstat.tcps_socachemiss);
254 lprint(" %6d UDP socket cache misses\r\n", udpstat.udpps_pcbcachemiss);
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| tcp_var.h | 221 u_long tcps_socachemiss; /* tcp_last_so misses */
|
| /external/qemu/slirp-android/ |
| debug.c | 164 lprint(" %6d searches for connection stats (%d misses)\r\n",
232 lprint(" %6d TCP cache misses\r\n", tcpstat.tcps_socachemiss);
250 lprint(" %6d UDP socket cache misses\r\n", udpstat.udpps_pcbcachemiss);
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| tcp_var.h | 225 u_long tcps_socachemiss; /* tcp_last_so misses */
|
| /frameworks/base/media/tests/MediaFrameworkTest/src/com/android/mediaframeworktest/unit/ |
| MediaPlayerMetadataParserTest.java | 131 // misses metadata id and metadata type.
140 // misses metadata type
158 // misses payload
|
| /prebuilt/linux-x86/oprofile/arm/armv7/ |
| events | 5 event:0x01 counters:1,2,3,4 um:zero minimum:500 name:IFETCH_MISS : Instruction fetch misses from cache or normal cacheable memory
6 event:0x02 counters:1,2,3,4 um:zero minimum:500 name:ITLB_MISS : Instruction fetch misses from TLB
|
| /prebuilt/linux-x86_64/oprofile/arm/armv7/ |
| events | 5 event:0x01 counters:1,2,3,4 um:zero minimum:500 name:IFETCH_MISS : Instruction fetch misses from cache or normal cacheable memory
6 event:0x02 counters:1,2,3,4 um:zero minimum:500 name:ITLB_MISS : Instruction fetch misses from TLB
|
| /dalvik/vm/compiler/ |
| Ralloc.c | 59 * code generation will handle misses. It might be worthwhile to collaborate
|
