Lines Matching refs:irq
52 #define GIC_SET_ENABLED(irq) s->irq_state[irq].enabled = 1
53 #define GIC_CLEAR_ENABLED(irq) s->irq_state[irq].enabled = 0
54 #define GIC_TEST_ENABLED(irq) s->irq_state[irq].enabled
55 #define GIC_SET_PENDING(irq, cm) s->irq_state[irq].pending |= (cm)
56 #define GIC_CLEAR_PENDING(irq, cm) s->irq_state[irq].pending &= ~(cm)
57 #define GIC_TEST_PENDING(irq, cm) ((s->irq_state[irq].pending & (cm)) != 0)
58 #define GIC_SET_ACTIVE(irq, cm) s->irq_state[irq].active |= (cm)
59 #define GIC_CLEAR_ACTIVE(irq, cm) s->irq_state[irq].active &= ~(cm)
60 #define GIC_TEST_ACTIVE(irq, cm) ((s->irq_state[irq].active & (cm)) != 0)
61 #define GIC_SET_MODEL(irq) s->irq_state[irq].model = 1
62 #define GIC_CLEAR_MODEL(irq) s->irq_state[irq].model = 0
63 #define GIC_TEST_MODEL(irq) s->irq_state[irq].model
64 #define GIC_SET_LEVEL(irq, cm) s->irq_state[irq].level = (cm)
65 #define GIC_CLEAR_LEVEL(irq, cm) s->irq_state[irq].level &= ~(cm)
66 #define GIC_TEST_LEVEL(irq, cm) ((s->irq_state[irq].level & (cm)) != 0)
67 #define GIC_SET_TRIGGER(irq) s->irq_state[irq].trigger = 1
68 #define GIC_CLEAR_TRIGGER(irq) s->irq_state[irq].trigger = 0
69 #define GIC_TEST_TRIGGER(irq) s->irq_state[irq].trigger
70 #define GIC_GET_PRIORITY(irq, cpu) \
71 (((irq) < 32) ? s->priority1[irq][cpu] : s->priority2[(irq) - 32])
73 #define GIC_TARGET(irq) 1
75 #define GIC_TARGET(irq) s->irq_target[irq]
107 int irq;
121 for (irq = 0; irq < GIC_NIRQ; irq++) {
122 if (GIC_TEST_ENABLED(irq) && GIC_TEST_PENDING(irq, cm)) {
123 if (GIC_GET_PRIORITY(irq, cpu) < best_prio) {
124 best_prio = GIC_GET_PRIORITY(irq, cpu);
125 best_irq = irq;
133 DPRINTF("Raised pending IRQ %d\n", best_irq);
142 gic_set_pending_private(gic_state *s, int cpu, int irq)
146 if (GIC_TEST_PENDING(irq, cm))
149 DPRINTF("Set %d pending cpu %d\n", irq, cpu);
150 GIC_SET_PENDING(irq, cm);
154 /* Process a change in an external IRQ input. */
155 static void gic_set_irq(void *opaque, int irq, int level)
159 irq += 32;
160 if (level == GIC_TEST_LEVEL(irq, ALL_CPU_MASK))
164 GIC_SET_LEVEL(irq, ALL_CPU_MASK);
165 if (GIC_TEST_TRIGGER(irq) || GIC_TEST_ENABLED(irq)) {
166 DPRINTF("Set %d pending mask %x\n", irq, GIC_TARGET(irq));
167 GIC_SET_PENDING(irq, GIC_TARGET(irq));
170 GIC_CLEAR_LEVEL(irq, ALL_CPU_MASK);
175 static void gic_set_running_irq(gic_state *s, int cpu, int irq)
177 s->running_irq[cpu] = irq;
178 if (irq == 1023) {
181 s->running_priority[cpu] = GIC_GET_PRIORITY(irq, cpu);
193 DPRINTF("ACK no pending IRQ\n");
205 static void gic_complete_irq(gic_state * s, int cpu, int irq)
209 DPRINTF("EOI %d\n", irq);
211 return; /* No active IRQ. */
212 if (irq != 1023) {
215 if (!GIC_TEST_TRIGGER(irq) && GIC_TEST_ENABLED(irq)
216 && GIC_TEST_LEVEL(irq, cm) && (GIC_TARGET(irq) & cm) != 0) {
217 DPRINTF("Set %d pending mask %x\n", irq, cm);
218 GIC_SET_PENDING(irq, cm);
222 if (irq != s->running_irq[cpu]) {
223 /* Complete an IRQ that is not currently running. */
226 if (s->last_active[tmp][cpu] == irq) {
227 s->last_active[tmp][cpu] = s->last_active[irq][cpu];
236 /* Complete the current running IRQ. */
245 int irq;
266 irq = (offset - 0x100) * 8;
268 irq = (offset - 0x180) * 8;
269 irq += GIC_BASE_IRQ;
270 if (irq >= GIC_NIRQ)
274 if (GIC_TEST_ENABLED(irq + i)) {
281 irq = (offset - 0x200) * 8;
283 irq = (offset - 0x280) * 8;
284 irq += GIC_BASE_IRQ;
285 if (irq >= GIC_NIRQ)
288 mask = (irq < 32) ? cm : ALL_CPU_MASK;
290 if (GIC_TEST_PENDING(irq + i, mask)) {
296 irq = (offset - 0x300) * 8 + GIC_BASE_IRQ;
297 if (irq >= GIC_NIRQ)
300 mask = (irq < 32) ? cm : ALL_CPU_MASK;
302 if (GIC_TEST_ACTIVE(irq + i, mask)) {
308 irq = (offset - 0x400) + GIC_BASE_IRQ;
309 if (irq >= GIC_NIRQ)
311 res = GIC_GET_PRIORITY(irq, cpu);
315 irq = (offset - 0x800) + GIC_BASE_IRQ;
316 if (irq >= GIC_NIRQ)
318 if (irq >= 29 && irq <= 31) {
321 res = GIC_TARGET(irq);
325 irq = (offset - 0xc00) * 2 + GIC_BASE_IRQ;
326 if (irq >= GIC_NIRQ)
330 if (GIC_TEST_MODEL(irq + i))
332 if (GIC_TEST_TRIGGER(irq + i))
378 int irq;
398 irq = (offset - 0x100) * 8 + GIC_BASE_IRQ;
399 if (irq >= GIC_NIRQ)
401 if (irq < 16)
405 int mask = (irq < 32) ? (1 << cpu) : GIC_TARGET(irq);
406 if (!GIC_TEST_ENABLED(irq + i))
407 DPRINTF("Enabled IRQ %d\n", irq + i);
408 GIC_SET_ENABLED(irq + i);
409 /* If a raised level triggered IRQ enabled then mark
411 if (GIC_TEST_LEVEL(irq + i, mask)
412 && !GIC_TEST_TRIGGER(irq + i)) {
413 DPRINTF("Set %d pending mask %x\n", irq + i, mask);
414 GIC_SET_PENDING(irq + i, mask);
420 irq = (offset - 0x180) * 8 + GIC_BASE_IRQ;
421 if (irq >= GIC_NIRQ)
423 if (irq < 16)
427 if (GIC_TEST_ENABLED(irq + i))
428 DPRINTF("Disabled IRQ %d\n", irq + i);
429 GIC_CLEAR_ENABLED(irq + i);
434 irq = (offset - 0x200) * 8 + GIC_BASE_IRQ;
435 if (irq >= GIC_NIRQ)
437 if (irq < 16)
438 irq = 0;
442 GIC_SET_PENDING(irq + i, GIC_TARGET(irq));
447 irq = (offset - 0x280) * 8 + GIC_BASE_IRQ;
448 if (irq >= GIC_NIRQ)
455 GIC_CLEAR_PENDING(irq + i, ALL_CPU_MASK);
463 irq = (offset - 0x400) + GIC_BASE_IRQ;
464 if (irq >= GIC_NIRQ)
466 if (irq < 32) {
467 s->priority1[irq][cpu] = value;
469 s->priority2[irq - 32] = value;
474 irq = (offset - 0x800) + GIC_BASE_IRQ;
475 if (irq >= GIC_NIRQ)
477 if (irq < 29)
479 else if (irq < 32)
481 s->irq_target[irq] = value & ALL_CPU_MASK;
484 irq = (offset - 0xc00) * 4 + GIC_BASE_IRQ;
485 if (irq >= GIC_NIRQ)
487 if (irq < 32)
491 GIC_SET_MODEL(irq + i);
493 GIC_CLEAR_MODEL(irq + i);
496 GIC_SET_TRIGGER(irq + i);
498 GIC_CLEAR_TRIGGER(irq + i);
533 int irq;
537 irq = value & 0x3ff;
553 GIC_SET_PENDING(irq, mask);
