Lines Matching defs:op1
621 static void gen_arm_parallel_addsub(int op1, int op2, TCGv a, TCGv b)
625 switch (op1) {
666 static void gen_thumb2_parallel_addsub(int op1, int op2, TCGv a, TCGv b)
670 switch (op1) {
4068 static inline void gen_neon_addl_saturate(TCGv_i64 op0, TCGv_i64 op1, int size)
4071 case 1: gen_helper_neon_addl_saturate_s32(op0, cpu_env, op0, op1); break;
4072 case 2: gen_helper_neon_addl_saturate_s64(op0, cpu_env, op0, op1); break;
5604 int op1 = (insn >> 21) & 7;
5610 if (op1 == 6 && crn == 0 && crm == 0 && op2 == 0) {
5618 if (op1 == 6 && crn == 1 && crm == 0 && op2 == 0) {
5627 fprintf(stderr, "Unknown cp14 read op1:%d crn:%d crm:%d op2:%d\n",
5628 op1, crn, crm, op2);
5636 int op1 = (insn >> 21) & 7;
5642 if (op1 == 6 && crn == 0 && crm == 0 && op2 == 0) {
5651 if (op1 == 6 && crn == 1 && crm == 0 && op2 == 0) {
5660 fprintf(stderr, "Unknown cp14 write op1:%d crn:%d crm:%d op2:%d\n",
5661 op1, crn, crm, op2);
5799 unsigned int cond, insn, val, op1, i, shift, rm, rs, rn, rd, sh;
5894 op1 = (insn & 0x1f);
5895 if (op1 == (env->uncached_cpsr & CPSR_M)) {
5899 gen_helper_get_r13_banked(addr, cpu_env, tcg_const_i32(op1));
5928 if (op1 == (env->uncached_cpsr & CPSR_M)) {
5931 gen_helper_set_r13_banked(cpu_env, tcg_const_i32(op1), cpu_T[1]);
6086 op1 = (insn >> 21) & 3;
6091 if (op1 & 1) {
6094 i = ((op1 & 2) != 0);
6100 if (op1 & 2) {
6112 if (op1 == 1) {
6116 } else if (op1 == 3) {
6127 if (op1 == 1) {
6137 if (op1 != 1)
6152 if (op1 & 2)
6154 if (op1 & 1)
6174 if (op1 == 1) {
6198 if (op1 == 2) {
6205 if (op1 == 0) {
6222 op1 = (insn >> 21) & 0xf;
6224 logic_cc = table_logic_cc[op1] & set_cc;
6253 if (op1 != 0x0f && op1 != 0x0d) {
6260 switch(op1) {
6395 if (op1 != 0x0f && op1 != 0x0d) {
6400 op1 = (insn >> 24) & 0xf;
6401 switch(op1) {
6407 if (op1 == 0x0) {
6412 op1 = (insn >> 20) & 0xf;
6413 switch (op1) {
6461 op1 = (insn >> 21) & 0x3;
6462 if (op1)
6470 switch (op1) {
6498 switch (op1) {
6625 op1 = (insn >> 20) & 7;
6629 if ((op1 & 3) == 0 || sh == 5 || sh == 6)
6631 gen_arm_parallel_addsub(op1, sh, tmp, tmp2);
6705 op1 = (insn >> 20) & 7;
6706 switch (op1) {
6717 if ((op1 & 3) == 0) {
6798 op1 = ((insn >> 17) & 0x38) | ((insn >> 5) & 7);
6799 switch (op1) {
6841 if (op1 & 0x20) {
6862 if (op1 == 0x7 && ((insn & sh) == sh))
