Lines Matching defs:Operand
205 // Implementation of Operand and MemOperand
208 Operand::Operand(Handle<Object> handle) {
224 Operand::Operand(Register rm, ShiftOp shift_op, int shift_imm) {
240 Operand::Operand(Register rm, ShiftOp shift_op, Register rs) {
291 I = 1 << 25, // immediate shifter operand (or not)
635 const Operand& x) {
644 // The immediate operand cannot be encoded as a shifter operand, so load
655 addrmod1(instr, rn, rd, Operand(ip));
689 mov(ip, Operand(x.offset_), LeaveCC,
723 mov(ip, Operand(x.offset_), LeaveCC,
734 mov(ip, Operand(x.rm_, x.shift_op_, x.shift_imm_), LeaveCC,
868 void Assembler::ubfx(Register dst, Register src1, const Operand& src2,
869 const Operand& src3, Condition cond) {
878 void Assembler::and_(Register dst, Register src1, const Operand& src2,
884 void Assembler::eor(Register dst, Register src1, const Operand& src2,
890 void Assembler::sub(Register dst, Register src1, const Operand& src2,
896 void Assembler::rsb(Register dst, Register src1, const Operand& src2,
902 void Assembler::add(Register dst, Register src1, const Operand& src2,
908 // add(sp, sp, Operand(kPointerSize));
925 void Assembler::adc(Register dst, Register src1, const Operand& src2,
931 void Assembler::sbc(Register dst, Register src1, const Operand& src2,
937 void Assembler::rsc(Register dst, Register src1, const Operand& src2,
943 void Assembler::tst(Register src1, const Operand& src2, Condition cond) {
948 void Assembler::teq(Register src1, const Operand& src2, Condition cond) {
953 void Assembler::cmp(Register src1, const Operand& src2, Condition cond) {
958 void Assembler::cmn(Register src1, const Operand& src2, Condition cond) {
963 void Assembler::orr(Register dst, Register src1, const Operand& src2,
969 void Assembler::mov(Register dst, const Operand& src, SBit s, Condition cond) {
977 void Assembler::bic(Register dst, Register src1, const Operand& src2,
983 void Assembler::mvn(Register dst, const Operand& src, SBit s, Condition cond) {
1073 void Assembler::msr(SRegisterFieldMask fields, const Operand& src,
1083 // Immediate operand cannot be encoded, load it first to register ip.
1086 msr(fields, Operand(ip), cond);
1609 mov(dst, Operand(x.rn_), s, cond);
1611 sub(dst, x.rn_, Operand(x.offset_), s, cond);
1613 add(dst, x.rn_, Operand(x.offset_), s, cond);
1620 mov(dst, Operand(x.rn_), s, cond);
1622 sub(dst, x.rn_, Operand(x.rm_, x.shift_op_, x.shift_imm_), s, cond);
1624 add(dst, x.rn_, Operand(x.rm_, x.shift_op_, x.shift_imm_), s, cond);
