Lines Matching refs:regT1
56 emitLoad(src, regT1, regT0);
58 Jump srcNotInt = branch32(NotEqual, regT1, Imm32(JSValue::Int32Tag));
67 addSlowCase(branch32(Above, regT1, Imm32(JSValue::LowestTag)));
69 xor32(Imm32(1 << 31), regT1);
70 store32(regT1, tagFor(dst));
85 stubCall.addArgument(regT1, regT0);
104 emitLoad(op1, regT1, regT0);
105 notInt32Op1.append(branch32(NotEqual, regT1, Imm32(JSValue::Int32Tag)));
108 emitLoad2(op1, regT1, regT0, op2, regT3, regT2);
109 notInt32Op1.append(branch32(NotEqual, regT1, Imm32(JSValue::Int32Tag)));
167 emitLoad(op1, regT1, regT0);
168 notInt32Op1.append(branch32(NotEqual, regT1, Imm32(JSValue::Int32Tag)));
171 emitLoad2(op1, regT1, regT0, op2, regT3, regT2);
172 notInt32Op1.append(branch32(NotEqual, regT1, Imm32(JSValue::Int32Tag)));
230 emitLoad(op1, regT1, regT0);
231 notInt32Op1.append(branch32(NotEqual, regT1, Imm32(JSValue::Int32Tag)));
234 emitLoad2(op1, regT1, regT0, op2, regT3, regT2);
235 notInt32Op1.append(branch32(NotEqual, regT1, Imm32(JSValue::Int32Tag)));
287 emitLoad(op1, regT1, regT0);
288 addSlowCase(branch32(NotEqual, regT1, Imm32(JSValue::Int32Tag)));
294 emitLoad2(op1, regT1, regT0, op2, regT3, regT2);
296 addSlowCase(branch32(NotEqual, regT1, Imm32(JSValue::Int32Tag)));
327 emitLoad(op1, regT1, regT0);
328 addSlowCase(branch32(NotEqual, regT1, Imm32(JSValue::Int32Tag)));
334 emitLoad2(op1, regT1, regT0, op2, regT3, regT2);
336 addSlowCase(branch32(NotEqual, regT1, Imm32(JSValue::Int32Tag)));
369 emitLoad(op, regT1, regT0);
370 addSlowCase(branch32(NotEqual, regT1, Imm32(JSValue::Int32Tag)));
376 emitLoad2(op1, regT1, regT0, op2, regT3, regT2);
377 addSlowCase(branch32(NotEqual, regT1, Imm32(JSValue::Int32Tag)));
410 emitLoad(op, regT1, regT0);
411 addSlowCase(branch32(NotEqual, regT1, Imm32(JSValue::Int32Tag)));
417 emitLoad2(op1, regT1, regT0, op2, regT3, regT2);
418 addSlowCase(branch32(NotEqual, regT1, Imm32(JSValue::Int32Tag)));
451 emitLoad(op, regT1, regT0);
452 addSlowCase(branch32(NotEqual, regT1, Imm32(JSValue::Int32Tag)));
458 emitLoad2(op1, regT1, regT0, op2, regT3, regT2);
459 addSlowCase(branch32(NotEqual, regT1, Imm32(JSValue::Int32Tag)));
488 emitLoad(src, regT1, regT0);
489 addSlowCase(branch32(NotEqual, regT1, Imm32(JSValue::Int32Tag)));
502 stubCall.addArgument(regT1, regT0);
513 emitLoad(srcDst, regT1, regT0);
514 addSlowCase(branch32(NotEqual, regT1, Imm32(JSValue::Int32Tag)));
547 emitLoad(srcDst, regT1, regT0);
548 addSlowCase(branch32(NotEqual, regT1, Imm32(JSValue::Int32Tag)));
580 emitLoad(srcDst, regT1, regT0);
582 addSlowCase(branch32(NotEqual, regT1, Imm32(JSValue::Int32Tag)));
605 emitLoad(srcDst, regT1, regT0);
607 addSlowCase(branch32(NotEqual, regT1, Imm32(JSValue::Int32Tag)));
651 emitLoad2(op1, regT1, regT0, op2, regT3, regT2);
652 notInt32Op1.append(branch32(NotEqual, regT1, Imm32(JSValue::Int32Tag)));
674 emitLoad(op, regT1, regT0);
675 Jump notInt32 = branch32(NotEqual, regT1, Imm32(JSValue::Int32Tag));
688 addSlowCase(branch32(Above, regT1, Imm32(JSValue::LowestTag)));
760 emitLoad2(op1, regT1, regT0, op2, regT3, regT2);
761 notInt32Op1.append(branch32(NotEqual, regT1, Imm32(JSValue::Int32Tag)));
783 emitLoad(op, regT1, regT0);
784 Jump notInt32 = branch32(NotEqual, regT1, Imm32(JSValue::Int32Tag));
797 addSlowCase(branch32(Above, regT1, Imm32(JSValue::LowestTag)));
854 addSlowCase(branch32(Above, regT1, Imm32(JSValue::LowestTag)));
983 emitLoad2(op1, regT1, regT0, op2, regT3, regT2);
984 notInt32Op1.append(branch32(NotEqual, regT1, Imm32(JSValue::Int32Tag)));
1065 emitLoad2(op1, regT1, regT0, op2, regT3, regT2);
1067 notInt32Op1.append(branch32(NotEqual, regT1, Imm32(JSValue::Int32Tag)));
1191 emitLoad2(op1, regT1, regT0, op2, regT3, regT2);
1192 addSlowCase(branch32(NotEqual, regT1, Imm32(JSValue::Int32Tag)));
1392 emitGetVirtualRegister(op2, regT1);
1393 emitJumpSlowCaseIfNotImmediateInteger(regT1);
1399 addJump(branch32(LessThanOrEqual, regT1, Imm32(op1imm)), target);
1401 emitGetVirtualRegisters(op1, regT0, op2, regT1);
1403 emitJumpSlowCaseIfNotImmediateInteger(regT1);
1405 addJump(branch32(GreaterThanOrEqual, regT0, regT1), target);
1439 move(Imm32(op2imm), regT1);
1440 regT1, fpRegT1);
1466 Jump fail1 = emitJumpIfNotImmediateNumber(regT1);
1467 addPtr(tagTypeNumberRegister, regT1);
1468 movePtrToDouble(regT1, fpRegT1);
1472 fail1 = emitJumpIfNotJSCell(regT1);
1474 Jump fail2 = checkStructure(regT1, m_globalData->numberStructure.get());
1475 loadDouble(Address(regT1, OBJECT_OFFSETOF(JSNumberCell, m_value)), fpRegT1);
1498 stubCall.addArgument(regT1);
1508 Jump fail2 = emitJumpIfNotImmediateNumber(regT1);
1509 Jump fail3 = emitJumpIfImmediateInteger(regT1);
1511 addPtr(tagTypeNumberRegister, regT1);
1513 movePtrToDouble(regT1, fpRegT1);
1521 fail2 = emitJumpIfNotJSCell(regT1);
1524 Jump fail4 = checkStructure(regT1, m_globalData->numberStructure.get());
1526 loadDouble(Address(regT1, OBJECT_OFFSETOF(JSNumberCell, m_value)), fpRegT1);
1550 stubCall.addArgument(regT1);
1577 emitGetVirtualRegister(op2, regT1);
1578 emitJumpSlowCaseIfNotImmediateInteger(regT1);
1584 addJump(branch32(GreaterThan, regT1, Imm32(op1imm)), target);
1586 emitGetVirtualRegisters(op1, regT0, op2, regT1);
1588 emitJumpSlowCaseIfNotImmediateInteger(regT1);
1590 addJump(branch32(LessThan, regT0, regT1), target);
1624 move(Imm32(op2imm), regT1);
1625 convertInt32ToDouble(regT1, fpRegT1);
1651 Jump fail1 = emitJumpIfNotImmediateNumber(regT1);
1652 addPtr(tagTypeNumberRegister, regT1);
1653 movePtrToDouble(regT1, fpRegT1);
1657 fail1 = emitJumpIfNotJSCell(regT1);
1659 Jump fail2 = checkStructure(regT1, m_globalData->numberStructure.get());
1660 loadDouble(Address(regT1, OBJECT_OFFSETOF(JSNumberCell, m_value)), fpRegT1);
1683 stubCall.addArgument(regT1);
1693 Jump fail2 = emitJumpIfNotImmediateNumber(regT1);
1694 Jump fail3 = emitJumpIfImmediateInteger(regT1);
1696 addPtr(tagTypeNumberRegister, regT1);
1698 movePtrToDouble(regT1, fpRegT1);
1706 fail2 = emitJumpIfNotJSCell(regT1);
1709 Jump fail4 = checkStructure(regT1, m_globalData->numberStructure.get());
1711 loadDouble(Address(regT1, OBJECT_OFFSETOF(JSNumberCell, m_value)), fpRegT1);
1735 stubCall.addArgument(regT1);
1762 emitGetVirtualRegister(op2, regT1);
1763 emitJumpSlowCaseIfNotImmediateInteger(regT1);
1769 addJump(branch32(LessThan, regT1, Imm32(op1imm)), target);
1771 emitGetVirtualRegisters(op1, regT0, op2, regT1);
1773 emitJumpSlowCaseIfNotImmediateInteger(regT1);
1775 addJump(branch32(GreaterThan, regT0, regT1), target);
1809 move(Imm32(op2imm), regT1);
1810 convertInt32ToDouble(regT1, fpRegT1);
1836 Jump fail1 = emitJumpIfNotImmediateNumber(regT1);
1837 addPtr(tagTypeNumberRegister, regT1);
1838 movePtrToDouble(regT1, fpRegT1);
1842 fail1 = emitJumpIfNotJSCell(regT1);
1844 Jump fail2 = checkStructure(regT1, m_globalData->numberStructure.get());
1845 loadDouble(Address(regT1, OBJECT_OFFSETOF(JSNumberCell, m_value)), fpRegT1);
1868 stubCall.addArgument(regT1);
1878 Jump fail2 = emitJumpIfNotImmediateNumber(regT1);
1879 Jump fail3 = emitJumpIfImmediateInteger(regT1);
1881 addPtr(tagTypeNumberRegister, regT1);
1883 movePtrToDouble(regT1, fpRegT1);
1891 fail2 = emitJumpIfNotJSCell(regT1);
1894 Jump fail4 = checkStructure(regT1, m_globalData->numberStructure.get());
1896 loadDouble(Address(regT1
1920 stubCall.addArgument(regT1);
1955 emitGetVirtualRegisters(op1, regT0, op2, regT1);
1956 andPtr(regT1, regT0);
1982 stubCall.addArgument(regT1);
1993 move(regT0, regT1);
1996 addSlowCase(branchAdd32(Overflow, Imm32(1), regT1));
1997 emitFastArithIntToImmNoCheck(regT1, regT1);
1999 addSlowCase(branchAdd32(Overflow, Imm32(1 << JSImmediate::IntegerPayloadShift), regT1));
2000 signExtend32ToPtr(regT1, regT1);
2002 emitPutVirtualRegister(srcDst, regT1);
2025 move(regT0, regT1);
2028 addSlowCase(branchSub32(Zero, Imm32(1), regT1));
2029 emitFastArithIntToImmNoCheck(regT1, regT1);
2031 addSlowCase(branchSub32(Zero, Imm32(1 << JSImmediate::IntegerPayloadShift), regT1));
2032 signExtend32ToPtr(regT1, regT1);
2034 emitPutVirtualRegister(srcDst, regT1);
2214 emitGetVirtualRegisters(op1, regT0, op2, regT1);
2216 emitJumpSlowCaseIfNotImmediateInteger(regT1);
2218 addSlowCase(branchAdd32(Overflow, regT1, regT0));
2220 addSlowCase(branchSub32(Overflow, regT1, regT0));
2223 addSlowCase(branchMul32(Overflow, regT1, regT0));
2254 emitGetVirtualRegister(op2, regT1);
2257 stubCall.addArgument(regT1);
2265 emitGetVirtualRegister(op1, regT1);
2266 convertInt32ToDouble(regT1, fpRegT1);
2273 emitGetVirtualRegister(op2, regT1);
2274 convertInt32ToDouble(regT1, fpRegT1);
2283 emitJumpIfNotImmediateNumber(regT1).linkTo(stubFunctionCall, this);
2286 Jump op2isDouble = emitJumpIfNotImmediateInteger(regT1);
2287 convertInt32ToDouble(regT1, fpRegT2);
2293 emitJumpIfNotImmediateNumber(regT1).linkTo(stubFunctionCall, this);
2296 addPtr(tagTypeNumberRegister, regT1);
2297 movePtrToDouble(regT1, fpRegT2);
2428 emitGetVirtualRegister(op2, regT1);
2429 addPtr(tagTypeNumberRegister, regT1);
2430 movePtrToDouble(regT1, fpRegT1);
2434 emitGetVirtualRegister(op2, regT1);
2436 emitJumpSlowCaseIfNotImmediateNumber(regT1);
2437 Jump notInt = emitJumpIfNotImmediateInteger(regT1);
2438 convertInt32ToDouble(regT1, fpRegT1);
2441 addPtr(tagTypeNumberRegister, regT1);
2442 movePtrToDouble(regT1, fpRegT1);
2512 emitGetVirtualRegisters(src1, regT0, src2, regT1);
2518 Jump op2imm = emitJumpIfImmediateInteger(regT1);
2520 emitJumpSlowCaseIfNotJSCell(regT1, src2);
2521 addSlowCase(checkStructure(regT1, numberStructure));
2542 addDouble(Address(regT1, OBJECT_OFFSETOF(JSNumberCell, m_value)), fpRegT0);
2544 subDouble(Address(regT1, OBJECT_OFFSETOF(JSNumberCell, m_value)), fpRegT0);
2547 mulDouble(Address(regT1, OBJECT_OFFSETOF(JSNumberCell, m_value)), fpRegT0);
2551 storeDouble(fpRegT0, Address(regT1, OBJECT_OFFSETOF(JSNumberCell, m_value)));
2552 move(regT1, regT0);
2572 Jump op2imm = emitJumpIfImmediateInteger(regT1);
2574 emitJumpSlowCaseIfNotJSCell(regT1, src2);
2575 addSlowCase(checkStructure(regT1, numberStructure));
2579 loadDouble(Address(regT1, OBJECT_OFFSETOF(JSNumberCell, m_value)), fpRegT1);
2583 emitFastArithImmToInt(regT1);
2584 convertInt32ToDouble(regT1, fpRegT1);
2607 emitJumpSlowCaseIfNotImmediateInteger(regT1);
2609 emitJumpSlowCaseIfNotImmediateIntegers(regT0, regT1, regT2);
2613 addSlowCase(branchAdd32(Overflow, regT1, regT0));
2615 addSlowCase(branchSub32(Overflow, regT1, regT0));
2621 emitFastArithImmToInt(regT1);
2623 Jump op2NonZero = branchTest32(NonZero, regT1);
2628 addSlowCase(branchAdd32(Signed, regT1, regT2));
2631 addSlowCase(branchMul32(Overflow, regT1, regT0));
