Lines Matching refs:pTxn
168 #define HW_INIT_PTXN_SET(pHwInit, pTxn) pTxn = (TTxnStruct*)&(pHwInit->aHwInitTxn[pHwInit->uTxnIndex].tTxnStruct);
170 #define BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, uAddr, uVal, uSize, direction, fCB, hCB) \
171 HW_INIT_PTXN_SET(pHwInit, pTxn) \
172 TXN_PARAM_SET_DIRECTION(pTxn, direction); \
174 BUILD_TTxnStruct(pTxn, uAddr, &(pHwInit->aHwInitTxn[pHwInit->uTxnIndex].uData), uSize, fCB, hCB)
176 #define BUILD_HW_INIT_FW_STATIC_TXN(pHwInit, pTxn, uAddr, fCB, hCB) \
177 HW_INIT_PTXN_SET(pHwInit, pTxn) \
178 TXN_PARAM_SET_DIRECTION(pTxn, TXN_DIRECTION_READ); \
179 BUILD_TTxnStruct(pTxn, uAddr, &(pHwInit->tFwStaticTxn.tFwStaticInfo), sizeof(FwStaticData_t), fCB, hCB)
181 #define BUILD_HW_INIT_FW_DL_TXN(pHwInit, pTxn, uAddr, uVal, uSize, direction, fCB, hCB) \
182 HW_INIT_PTXN_SET(pHwInit, pTxn) \
183 TXN_PARAM_SET_DIRECTION(pTxn, direction); \
184 BUILD_TTxnStruct(pTxn, uAddr, uVal, uSize, fCB, hCB)
483 TTxnStruct* pTxn;
509 HW_INIT_PTXN_SET(pHwInit, pTxn)
511 TXN_PARAM_SET(pTxn, TXN_LOW_PRIORITY, TXN_FUNC_ID_WLAN, TXN_DIRECTION_WRITE, TXN_INC_ADDR)
647 TTxnStruct *pTxn;
665 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, SCR_PAD8, 0xBABABABE,
667 twIf_Transact(pHwInit->hTwIf, pTxn);
684 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, PLL_PARAMETERS, clkVal,
686 twIf_Transact(pHwInit->hTwIf, pTxn);
691 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, PLL_PARAMETERS, 0,
693 status = twIf_Transact(pHwInit->hTwIf, pTxn);
708 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, WU_COUNTER_PAUSE, uData,
710 twIf_Transact(pHwInit->hTwIf, pTxn);
715 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL,
717 twIf_Transact(pHwInit->hTwIf, pTxn);
730 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, DRPW_SCRATCH_START, 0,
732 status = twIf_Transact(pHwInit->hTwIf, pTxn);
748 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, DRPW_SCRATCH_START, clkVal,
750 twIf_Transact(pHwInit->hTwIf, pTxn);
764 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, ACX_REG_INTERRUPT_MASK, ACX_INTR_ALL,
766 twIf_Transact(pHwInit->hTwIf, pTxn);
771 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, CHIP_ID, 0,
773 status = twIf_Transact(pHwInit->hTwIf, pTxn);
854 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, ACX_EEPROMLESS_IND_REG, ACX_EEPROMLESS_IND_REG,
856 twIf_Transact(pHwInit->hTwIf, pTxn);
867 TXN_PARAM_SET(pTxn, TXN_LOW_PRIORITY, TXN_FUNC_ID_WLAN, TXN_DIRECTION_WRITE, TXN_INC_ADDR)
868 BUILD_TTxnStruct(pTxn, ACX_REG_EE_START, &pHwInit->uRegister, REGISTER_SIZE, 0, NULL, NULL)
869 twIf_Transact(pHwInit->hTwIf, pTxn);*/
876 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, ACX_EEPROMLESS_IND_REG, USE_EEPROM,
878 twIf_Transact(pHwInit->hTwIf, pTxn);
886 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, CHIP_ID, 0,
888 status = twIf_Transact(pHwInit->hTwIf, pTxn);
911 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, SCR_PAD2, 0,
913 status = twIf_Transact(pHwInit->hTwIf, pTxn);
1056 TTxnStruct* pTxn;
1069 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, ACX_REG_ECPU_CONTROL, 0,
1071 status = twIf_Transact(pHwInit->hTwIf, pTxn);
1085 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, ACX_REG_ECPU_CONTROL, (pHwInit->uFinData | ECPU_CONTROL_HALT),
1087 twIf_Transact(pHwInit->hTwIf, pTxn);
1097 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, CHIP_ID, 0,
1099 status = twIf_Transact(pHwInit->hTwIf, pTxn);
1129 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, ACX_REG_INTERRUPT_NO_CLEAR, 0,
1131 status = twIf_Transact(pHwInit->hTwIf, pTxn);
1160 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, ACX_REG_INTERRUPT_ACK, ACX_INTR_INIT_COMPLETE,
1162 twIf_Transact(pHwInit->hTwIf, pTxn);
1225 BUILD_HW_INIT_FW_STATIC_TXN(pHwInit, pTxn, cmdMbox_GetMboxAddress (pTWD->hCmdMbox),
1227 status = twIf_Transact(pHwInit->hTwIf, pTxn);
1265 TTxnStruct* pTxn;
1270 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, REG_ENABLE_TX_RX, 0x0,
1272 status = twIf_Transact(pHwInit->hTwIf, pTxn);
1295 TTxnStruct* pTxn;
1356 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, (REGISTERS_BASE+pHwInit->uEEPROMRegAddr), val,
1358 status = twIf_Transact(pHwInit->hTwIf, pTxn);
1408 HW_INIT_PTXN_SET(pHwInit, pTxn)
1409 TXN_PARAM_SET_DIRECTION(pTxn, TXN_DIRECTION_WRITE);
1410 BUILD_TTxnStruct(pTxn, CMD_MBOX_ADDRESS, pHwInit->pEEPROMCurPtr, pHwInit->uEEPROMCurLen,
1414 status = twIf_Transact(pHwInit->hTwIf, pTxn);
1461 TTxnStruct* pTxn;
1544 BUILD_HW_INIT_FW_DL_TXN(pHwInit, pTxn, (pHwInit->uFwAddress + pHwInit->uBlockWriteNum * MAX_SDIO_BLOCK),
1547 TxnStatus = twIf_Transact(pHwInit->hTwIf, pTxn);
1579 BUILD_HW_INIT_FW_DL_TXN(pHwInit, pTxn, (pHwInit->uFwAddress + pHwInit->uBlockWriteNum * MAX_SDIO_BLOCK),
1582 TxnStatus = twIf_Transact(pHwInit->hTwIf, pTxn);
1641 TTxnStruct *pTxn;
1656 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, GPIO_SELECT, 0,
1658 status = twIf_Transact(pHwInit->hTwIf, pTxn);
1672 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, GPIO_SELECT, val,
1675 twIf_Transact(pHwInit->hTwIf, pTxn);
1694 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, OCP_POR_CTR, val,
1696 twIf_Transact(pHwInit->hTwIf, pTxn);
1700 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, OCP_CMD, 0x2,
1702 twIf_Transact(pHwInit->hTwIf, pTxn);
1711 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, OCP_DATA_RD, 0,
1713 status = twIf_Transact(pHwInit->hTwIf, pTxn);
1768 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, OCP_POR_CTR, value,
1770 twIf_Transact(pHwInit->hTwIf, pTxn);
1792 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, OCP_POR_WDATA, value,
1794 twIf_Transact(pHwInit->hTwIf, pTxn);
1798 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, OCP_CMD, 0x1,
1801 /*BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, INDIRECT_REG5, 0x1,
1804 status = twIf_Transact(pHwInit->hTwIf, pTxn);
1836 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, GPIO_OE_RADIO, 0,
1838 status = twIf_Transact(pHwInit->hTwIf, pTxn);
1851 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, GPIO_OE_RADIO, val,
1853 twIf_Transact(pHwInit->hTwIf, pTxn);
1857 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, GPIO_IN, 0,
1859 status = twIf_Transact(pHwInit->hTwIf, pTxn);
1952 TTxnStruct *pTxn;
1990 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, OCP_POR_CTR, val,
1993 twIf_Transact(pHwInit->hTwIf, pTxn);
1999 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, OCP_CMD, 0x2,
2001 twIf_Transact(pHwInit->hTwIf, pTxn);
2010 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, OCP_DATA_RD, 0,
2012 status = twIf_Transact(pHwInit->hTwIf, pTxn);
2070 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, OCP_POR_CTR, value,
2073 twIf_Transact(pHwInit->hTwIf, pTxn);
2087 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, OCP_POR_WDATA, val,
2089 twIf_Transact(pHwInit->hTwIf, pTxn);
2094 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, OCP_CMD, 0x1,
2096 status = twIf_Transact(pHwInit->hTwIf, pTxn);
2157 TTxnStruct *pTxn;
2168 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, OCP_POR_CTR, pHwInit->uTopRegAddr,
2170 twIf_Transact(pHwInit->hTwIf, pTxn);
2174 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, OCP_POR_WDATA, pHwInit->uTopRegValue,
2176 twIf_Transact(pHwInit->hTwIf, pTxn);
2180 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, OCP_CMD, 0x1,
2182 pHwInit->uTopStatus = twIf_Transact(pHwInit->hTwIf, pTxn);
2255 TTxnStruct *pTxn;
2267 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, OCP_POR_CTR, pHwInit->uTopRegAddr,
2269 twIf_Transact(pHwInit->hTwIf, pTxn);
2272 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, OCP_CMD, 0x2,
2274 twIf_Transact(pHwInit->hTwIf, pTxn);
2282 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, OCP_DATA_RD, 0,
2284 pHwInit->uTopStatus = twIf_Transact(pHwInit->hTwIf, pTxn);
