Lines Matching refs:pHwInit
152 #define HW_INIT_PTXN_SET(pHwInit, pTxn) pTxn = (TTxnStruct*)&(pHwInit->aHwInitTxn[pHwInit->uTxnIndex].tTxnStruct);
154 #define BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, uAddr, uVal, uSize, direction, fCB, hCB) \
155 HW_INIT_PTXN_SET(pHwInit, pTxn) \
157 pHwInit->aHwInitTxn[pHwInit->uTxnIndex].uData = (TI_UINT32)uVal; \
158 BUILD_TTxnStruct(pTxn, uAddr, &(pHwInit->aHwInitTxn[pHwInit->uTxnIndex].uData), uSize, fCB, hCB)
160 #define BUILD_HW_INIT_FW_STATIC_TXN(pHwInit, pTxn, uAddr, fCB, hCB) \
161 HW_INIT_PTXN_SET(pHwInit, pTxn) \
163 BUILD_TTxnStruct(pTxn, uAddr, &(pHwInit->tFwStaticTxn.tFwStaticInfo), sizeof(FwStaticData_t), fCB, hCB)
165 #define BUILD_HW_INIT_FW_DL_TXN(pHwInit, pTxn, uAddr, uVal, uSize, direction, fCB, hCB) \
166 HW_INIT_PTXN_SET(pHwInit, pTxn) \
181 #define EXCEPT(phwinit,status) \
190 TWD_FinalizeOnFailure (phwinit->hTWD); \
196 #define EXCEPT_I(phwinit,status) \
202 phwinit->uInitSeqStatus = status; \
205 TWD_FinalizeOnFailure (phwinit->hTWD); \
211 #define EXCEPT_L(phwinit,status) \
217 phwinit->DownloadStatus = status; \
220 phwinit->DownloadStatus = status; \
221 TWD_FinalizeOnFailure (phwinit->hTWD); \
366 static void hwInit_SetPartition (THwInit *pHwInit,
397 THwInit *pHwInit;
400 pHwInit = os_memoryAlloc (hOs, sizeof(THwInit));
402 if (pHwInit == NULL)
409 os_memoryZero (hOs, pHwInit, sizeof(THwInit));
411 pHwInit->hOs = hOs;
413 return (TI_HANDLE)pHwInit;
431 THwInit *pHwInit = (THwInit *)hHwInit;
434 os_memoryFree (pHwInit->hOs, pHwInit, sizeof(THwInit));
455 THwInit *pHwInit = (THwInit *)hHwInit;
462 pHwInit->hReport = hReport;
463 pHwInit->hTWD = hTWD;
464 pHwInit->hTwIf = ((TTwd *)hTWD)->hTwIf;
465 pHwInit->hOs = ((TTwd *)hTWD)->hOs;
466 pHwInit->fInitHwCb = fInitHwCb;
467 pHwInit->fFinalizeDownload = fFinalizeDownload;
468 pHwInit->hFinalizeDownload = hFinalizeDownload;
470 SET_DEF_NVS(pHwInit->aDefaultNVS)
475 pHwInit->aDefaultNVS[3] = (u8)rand_mac;
476 pHwInit->aDefaultNVS[4] = (u8)(rand_mac >> 8);
477 pHwInit->aDefaultNVS[5] = (u8)(rand_mac >> 16);
480 for (pHwInit->uTxnIndex=0;pHwInit->uTxnIndex<MAX_HW_INIT_CONSECUTIVE_TXN;pHwInit->uTxnIndex++)
482 HW_INIT_PTXN_SET(pHwInit, pTxn)
487 TRACE0(pHwInit->hReport, REPORT_SEVERITY_INIT, ".....HwInit configured successfully\n");
495 THwInit *pHwInit = (THwInit *)hHwInit;
497 pHwInit->pEEPROMBuf = pbuf;
498 pHwInit->uEEPROMLen = length;
506 THwInit *pHwInit = (THwInit *)hHwInit;
513 pHwInit->pFwBuf = pFileInfo->pBuffer;
514 pHwInit->uFwLength = pFileInfo->uLength;
515 pHwInit->uFwAddress = pFileInfo->uAddress;
516 pHwInit->bFwBufLast = pFileInfo->bLast;
537 * \param pHwInit - The module's object
542 static void hwInit_SetPartition (THwInit *pHwInit,
545 TRACE7(pHwInit->hReport, REPORT_SEVERITY_INFORMATION, "hwInit_SetPartition: uMemAddr1=0x%x, MemSize1=0x%x uMemAddr2=0x%x, MemSize2=0x%x, uMemAddr3=0x%x, MemSize3=0x%x, uMemAddr4=0x%x, MemSize4=0x%x\n",pPartition[0].uMemAdrr, pPartition[0].uMemSize,pPartition[1].uMemAdrr, pPartition[1].uMemSize,pPartition[2].uMemAdrr, pPartition[2].uMemSize,pPartition[3].uMemAdrr );
548 twIf_SetPartition (pHwInit->hTwIf,pPartition);
566 THwInit *pHwInit = (THwInit *)hHwInit;
567 TTwd *pTWD = (TTwd *)pHwInit->hTWD;
578 pHwInit->DownloadStatus = TXN_STATUS_PENDING;
581 pHwInit->uInitStage = 0;
583 os_memoryCopy (pHwInit->hOs, &pHwInit->tBootAttr, &tBootAttr, sizeof(TBootAttr));
595 return pHwInit->DownloadStatus;
610 THwInit *pHwInit = (THwInit *)hHwInit;
614 TTwd *pTWD = (TTwd *) pHwInit->hTWD;
618 switch (pHwInit->uInitStage)
621 pHwInit->uInitStage++;
622 pHwInit->uTxnIndex = 0;
625 SET_WORK_PARTITION(pHwInit->aPartition)
626 hwInit_SetPartition (pHwInit,pHwInit->aPartition);
630 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, SCR_PAD8, 0xBABABABE,
632 twIf_Transact(pHwInit->hTwIf, pTxn);
633 pHwInit->uTxnIndex++;
649 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, PLL_PARAMETERS, clkVal,
651 twIf_Transact(pHwInit->hTwIf, pTxn);
653 pHwInit->uTxnIndex++;
656 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, PLL_PARAMETERS, 0,
658 status = twIf_Transact(pHwInit->hTwIf, pTxn);
660 EXCEPT (pHwInit, status)
663 pHwInit->uInitStage ++;
664 /* We don't zero pHwInit->uTxnIndex at the begining because we need it's value to the next transaction */
665 uData = pHwInit->aHwInitTxn[pHwInit->uTxnIndex].uData;
669 pHwInit->uTxnIndex = 0;
673 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, WU_COUNTER_PAUSE, uData,
675 twIf_Transact(pHwInit->hTwIf, pTxn);
677 pHwInit->uTxnIndex++;
680 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL,
682 twIf_Transact(pHwInit->hTwIf, pTxn);
685 os_StalluSec (pHwInit->hOs, 500);
688 SET_DRP_PARTITION(pHwInit->aPartition)
689 hwInit_SetPartition (pHwInit,pHwInit->aPartition);
691 pHwInit->uTxnIndex++;
695 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, DRPW_SCRATCH_START, 0,
697 status = twIf_Transact(pHwInit->hTwIf, pTxn);
699 EXCEPT (pHwInit, status)
702 pHwInit->uInitStage ++;
706 clkVal = pHwInit->aHwInitTxn[pHwInit->uTxnIndex].uData;
707 pHwInit->uTxnIndex = 0; /* Reset index only after getting the last read value! */
709 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, DRPW_SCRATCH_START, clkVal,
711 twIf_Transact(pHwInit->hTwIf, pTxn);
713 pHwInit->uTxnIndex++;
717 SET_WORK_PARTITION(pHwInit->aPartition)
718 hwInit_SetPartition (pHwInit,pHwInit->aPartition);
725 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, ACX_REG_INTERRUPT_MASK, ACX_INTR_ALL,
727 twIf_Transact(pHwInit->hTwIf, pTxn);
729 pHwInit->uTxnIndex++;
732 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, CHIP_ID, 0,
734 status = twIf_Transact(pHwInit->hTwIf, pTxn);
736 EXCEPT (pHwInit, status)
739 pHwInit->uInitStage ++;
741 /* We don't zero pHwInit->uTxnIndex at the begining because we need it's value to the next transaction */
742 pHwInit->uChipId = pHwInit->aHwInitTxn[pHwInit->uTxnIndex].uData;
745 if (pHwInit->uChipId == CHIP_ID_1273_PG10)
750 else if (pHwInit->uChipId == CHIP_ID_1273_PG20)
757 WLAN_OS_REPORT (("Error!! Found unknown Chip Id = 0x%x\n", pHwInit->uChipId));
768 pHwInit->uResetStage = 0;
769 pHwInit->uSelfClearTime = 0;
770 pHwInit->uBootData = 0;
771 status = hwInit_ResetSm (pHwInit);
773 EXCEPT (pHwInit, status)
776 pHwInit->uInitStage ++;
778 TRACE0(pHwInit->hReport, REPORT_SEVERITY_INIT , "TNET SOFT-RESET\n");
786 if (pHwInit->pEEPROMBuf)
789 pHwInit->uEEPROMCurLen = pHwInit->uEEPROMLen;
791 TRACE2(pHwInit->hReport, REPORT_SEVERITY_INIT , "EEPROM Image addr=0x%x, EEPROM Len=0x0x%x\n", pHwInit->pEEPROMBuf, pHwInit->uEEPROMLen);
793 pHwInit->pEEPROMBuf, pHwInit->uEEPROMLen));
798 pHwInit->uEEPROMCurLen = DEF_NVS_SIZE;
799 pHwInit->pEEPROMBuf = (TI_UINT8*)(&pHwInit->aDefaultNVS[0]);
800 WLAN_OS_REPORT (("pHwInit->uEEPROMCurLen: %x\n", pHwInit->uEEPROMCurLen));
805 pHwInit->pEEPROMCurPtr = pHwInit->pEEPROMBuf;
806 pHwInit->uEEPROMStage = 0;
809 EXCEPT (pHwInit, status)
812 pHwInit->uInitStage ++;
813 pHwInit->uTxnIndex = 0;
815 if (pHwInit->pEEPROMBuf)
818 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, ACX_EEPROMLESS_IND_REG, ACX_EEPROMLESS_IND_REG,
820 twIf_Transact(pHwInit->hTwIf, pTxn);
822 TRACE0(pHwInit->hReport, REPORT_SEVERITY_INIT , "DRIVER NVS BURST-READ\n");
830 /*pHwInit->uRegister = START_EEPROM_MGR;
832 BUILD_TTxnStruct(pTxn, ACX_REG_EE_START, &pHwInit->uRegister, REGISTER_SIZE, 0, NULL, NULL)
833 twIf_Transact(pHwInit->hTwIf, pTxn);*/
838 os_StalluSec (pHwInit->hOs, 40000);
840 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, ACX_EEPROMLESS_IND_REG, USE_EEPROM,
842 twIf_Transact(pHwInit->hTwIf, pTxn);
844 TRACE0(pHwInit->hReport, REPORT_SEVERITY_INIT , "STARTING EEPROM NVS BURST-READ\n");
847 pHwInit->uTxnIndex++;
850 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, CHIP_ID, 0,
852 status = twIf_Transact(pHwInit->hTwIf, pTxn);
854 EXCEPT (pHwInit, status)
857 pHwInit->uInitStage ++;
858 /* We don't zero pHwInit->uTxnIndex at the begining because we need it's value to the next transaction */
859 pHwInit->uBootData = pHwInit->aHwInitTxn[pHwInit->uTxnIndex].uData;
861 pHwInit->uTxnIndex = 0;
863 WLAN_OS_REPORT(("Chip ID is 0x%X.\n", pHwInit->uBootData));
865 if (pHwInit->uBootData == 0)
867 WLAN_OS_REPORT(("Cannot read ChipID stopping\n", pHwInit->uBootData));
868 TWD_FinalizeOnFailure (pHwInit->hTWD);
875 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, SCR_PAD2, 0,
877 status = twIf_Transact(pHwInit->hTwIf, pTxn);
878 EXCEPT (pHwInit, status)
881 pHwInit->uInitStage ++;
882 /* We don't zero pHwInit->uTxnIndex at the begining because we need it's value to the next transaction */
883 pHwInit->uBootData = pHwInit->aHwInitTxn[pHwInit->uTxnIndex].uData;
885 if (pHwInit->uBootData == 0xffffffff)
887 TRACE0(pHwInit->hReport, REPORT_SEVERITY_FATAL_ERROR , "Error in SCR_PAD2 register\n");
888 EXCEPT (pHwInit, TXN_STATUS_ERROR)
892 pHwInit->uInitSeqStage = 0;
893 pHwInit->uInitSeqStatus = TXN_STATUS_COMPLETE;
895 EXCEPT (pHwInit, status)
898 pHwInit->uInitStage++;
902 EXCEPT (pHwInit, status)
906 pHwInit->uInitStage++;
910 pHwInit->uTopRegValue &= FREF_CLK_TYPE_BITS;
911 pHwInit->uTopRegValue |= CLK_REQ_PRCM;
912 status = hwInit_InitTopRegisterWrite( hHwInit, 0x448, pHwInit->uTopRegValue);
913 EXCEPT (pHwInit, status)
917 pHwInit->uInitStage++;
921 EXCEPT (pHwInit, status)
925 pHwInit->uInitStage++;
928 pHwInit->uTopRegValue &= FREF_CLK_POLARITY_BITS;
929 pHwInit->uTopRegValue |= CLK_REQ_OUTN_SEL;
930 status = hwInit_InitTopRegisterWrite( hHwInit, 0xCB2, pHwInit->uTopRegValue);
931 EXCEPT (pHwInit, status)
935 pHwInit->uInitStage = 0;
938 pHwInit->DownloadStatus = TXN_STATUS_COMPLETE;
941 if (pHwInit->fInitHwCb)
943 (*pHwInit->fInitHwCb) (pHwInit->hTWD);
955 THwInit *pHwInit = (THwInit *)hHwInit;
961 EXCEPT (pHwInit, TXN_STATUS_ERROR)
964 if (pHwInit->pFwBuf)
966 TRACE0(pHwInit->hReport, REPORT_SEVERITY_INIT , "CPU halt -> download code\n");
969 pHwInit->uLoadStage = 0;
970 status = hwInit_LoadFwImageSm (pHwInit);
983 TRACE0(pHwInit->hReport, REPORT_SEVERITY_ERROR , "Firmware download failed!\n");
987 EXCEPT (pHwInit, status);
991 TRACE0(pHwInit->hReport, REPORT_SEVERITY_INIT , "Firmware not downloaded...\n");
993 EXCEPT (pHwInit, TXN_STATUS_ERROR)
1017 THwInit *pHwInit = (THwInit *)hHwInit;
1018 TTwd *pTWD = (TTwd *)pHwInit->hTWD;
1031 switch (pHwInit->uFinStage)
1034 pHwInit->uFinStage = 1;
1035 pHwInit->uTxnIndex = 0;
1039 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, ACX_REG_ECPU_CONTROL, 0,
1041 status = twIf_Transact(pHwInit->hTwIf, pTxn);
1043 EXCEPT (pHwInit, status)
1046 pHwInit->uFinStage ++;
1047 /* We don't zero pHwInit->uTxnIndex at the begining because we need it's value to the next transaction */
1048 pHwInit->uFinData = pHwInit->aHwInitTxn[pHwInit->uTxnIndex].uData;
1050 pHwInit->uTxnIndex = 0;
1055 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, ACX_REG_ECPU_CONTROL, (pHwInit->uFinData | ECPU_CONTROL_HALT),
1057 twIf_Transact(pHwInit->hTwIf, pTxn);
1065 pHwInit->uTxnIndex++;
1067 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, CHIP_ID, 0,
1069 status = twIf_Transact(pHwInit->hTwIf, pTxn);
1071 EXCEPT (pHwInit, status)
1074 pHwInit->uFinStage ++;
1075 pHwInit->uFinLoop = 0;
1077 /* We don't zero pHwInit->uTxnIndex at the begining because we need it's value to the next transaction */
1078 pHwInit->uFinData = pHwInit->aHwInitTxn[pHwInit->uTxnIndex].uData;
1080 TRACE1(pHwInit->hReport, REPORT_SEVERITY_INIT , "CHIP ID IS %x\n", pHwInit->uFinData);
1082 TRACE0(pHwInit->hReport, REPORT_SEVERITY_INIT , "Wait init complete\n");
1085 pHwInit->uTxnIndex = 0;
1090 if (pHwInit->uFinLoop < FIN_LOOP)
1092 pHwInit->uFinStage = 4;
1094 os_StalluSec (pHwInit->hOs, 50);
1097 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, ACX_REG_INTERRUPT_NO_CLEAR, 0,
1099 status = twIf_Transact(pHwInit->hTwIf, pTxn);
1101 EXCEPT (pHwInit, status)
1105 pHwInit->uFinStage = 5;
1110 /* We don't zero pHwInit->uTxnIndex at the begining because we need it's value to the next transaction */
1111 pHwInit->uFinData = pHwInit->aHwInitTxn[pHwInit->uTxnIndex].uData;
1113 pHwInit->uTxnIndex = 0;
1115 if (pHwInit->uFinData == 0xffffffff) /* error */
1117 TRACE0(pHwInit->hReport, REPORT_SEVERITY_ERROR , "Error reading hardware complete init indication\n");
1119 pHwInit->DownloadStatus = TXN_STATUS_ERROR;
1120 EXCEPT (pHwInit, TXN_STATUS_ERROR)
1123 if (IS_MASK_ON (pHwInit->uFinData, ACX_INTR_INIT_COMPLETE))
1125 pHwInit->uFinStage = 5;
1128 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, ACX_REG_INTERRUPT_ACK, ACX_INTR_INIT_COMPLETE,
1130 twIf_Transact(pHwInit->hTwIf, pTxn);
1136 pHwInit->uFinStage = 3;
1137 pHwInit->uFinLoop ++;
1142 pHwInit->uFinStage++;
1144 if (pHwInit->uFinLoop >= FIN_LOOP)
1146 TRACE0(pHwInit->hReport, REPORT_SEVERITY_ERROR , "Timeout waiting for the hardware to complete initialization\n");
1148 pHwInit->DownloadStatus = TXN_STATUS_ERROR;
1149 EXCEPT (pHwInit, TXN_STATUS_ERROR);
1152 TRACE0(pHwInit->hReport, REPORT_SEVERITY_INIT , "Firmware init complete...\n");
1162 EXCEPT (pHwInit, status)
1165 pHwInit->uFinStage++;
1171 EXCEPT (pHwInit, status);
1174 pHwInit->uFinStage++;
1175 pHwInit->uTxnIndex = 0;
1177 SET_WORK_PARTITION(pHwInit->aPartition)
1179 SET_WORK_PARTITION(pHwInit->aPartition)
1180 hwInit_SetPartition (pHwInit,pHwInit->aPartition);
1189 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, ACX_REG_INTERRUPT_MASK, (~uIntVect),
1191 twIf_Transact(pHwInit->hTwIf, pTxn);
1192 pHwInit->uTxnIndex++;
1195 BUILD_HW_INIT_FW_STATIC_TXN(pHwInit, pTxn, cmdMbox_GetMboxAddress (pTWD->hCmdMbox),
1197 status = twIf_Transact(pHwInit->hTwIf, pTxn);
1199 EXCEPT (pHwInit, status);
1204 pHwInit->uFinStage = 0;
1206 cmdBld_FinalizeDownload (pTWD->hCmdBld, &pHwInit->tBootAttr, &(pHwInit->tFwStaticTxn.tFwStaticInfo));
1209 pHwInit->DownloadStatus = TXN_STATUS_COMPLETE;
1233 THwInit *pHwInit = (THwInit *)hHwInit;
1237 pHwInit->uTxnIndex = 0;
1240 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, REG_ENABLE_TX_RX, 0x0,
1242 twIf_Transact(pHwInit->hTwIf, pTxn);
1244 pHwInit->uTxnIndex++;
1247 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, SPARE_A2, 0xFFFF,
1249 status = twIf_Transact(pHwInit->hTwIf, pTxn);
1268 THwInit *pHwInit = (THwInit *)hHwInit;
1274 pHwInit->uTxnIndex = 0;
1278 switch (pHwInit->uEEPROMStage)
1291 if ((pHwInit->uEEPROMRegAddr = pHwInit->pEEPROMCurPtr[1]) & 1)
1294 pHwInit->uEEPROMRegAddr &= 0xfe;
1296 pHwInit->uEEPROMRegAddr |= (TI_UINT32)pHwInit->pEEPROMCurPtr[2] << 8;
1298 pHwInit->uEEPROMBurstLen = pHwInit->pEEPROMCurPtr[0];
1299 pHwInit->pEEPROMCurPtr += 3;
1300 pHwInit->uEEPROMBurstLoop = 0;
1305 pHwInit->uEEPROMStage = 1;
1311 if (pHwInit->pEEPROMCurPtr[0] == 0)
1313 pHwInit->pEEPROMCurPtr += 7;
1315 pHwInit->uEEPROMCurLen -= (pHwInit->pEEPROMCurPtr - pHwInit->pEEPROMBuf + 1);
1316 pHwInit->uEEPROMCurLen = (pHwInit->uEEPROMCurLen + NVS_DATA_BUNDARY_ALIGNMENT - 1) & 0xfffffffc;
1318 pHwInit->uEEPROMStage = 2;
1323 if (pHwInit->uEEPROMBurstLoop < pHwInit->uEEPROMBurstLen)
1326 TI_UINT32 val = (pHwInit->pEEPROMCurPtr[0] |
1327 (pHwInit->pEEPROMCurPtr[1] << 8) |
1328 (pHwInit->pEEPROMCurPtr[2] << 16) |
1329 (pHwInit->pEEPROMCurPtr[3] << 24));
1331 TRACE2(pHwInit->hReport, REPORT_SEVERITY_INIT , "NVS::BurstRead: *(%08x) = %x\n", pHwInit->uEEPROMRegAddr, val);
1333 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, (REGISTERS_BASE+pHwInit->uEEPROMRegAddr), val,
1335 status = twIf_Transact(pHwInit->hTwIf, pTxn);
1337 pHwInit->uEEPROMStatus = status;
1338 pHwInit->uEEPROMRegAddr += WORD_SIZE;
1339 pHwInit->pEEPROMCurPtr += WORD_SIZE;
1341 pHwInit->uEEPROMStage = 1;
1342 pHwInit->uEEPROMBurstLoop ++;
1344 EXCEPT (pHwInit, status);
1349 pHwInit->uEEPROMStage = 0;
1357 pHwInit->uEEPROMStage = 3;
1360 SET_WORK_PARTITION(pHwInit->aPartition)
1361 hwInit_SetPartition (pHwInit,pHwInit->aPartition);
1365 TRACE0(pHwInit->hReport, REPORT_SEVERITY_INIT , "Reached TLV section\n");
1368 if (((TI_UINT32)pHwInit->pEEPROMCurPtr & WORD_ALIGNMENT_MASK) && (pHwInit->uEEPROMCurLen > 0) )
1370 uAddr = (TI_UINT8*)(((TI_UINT32)pHwInit->pEEPROMCurPtr & 0xFFFFFFFC)+WORD_SIZE);
1371 uDeltaLength = uAddr - pHwInit->pEEPROMCurPtr + 1;
1373 pHwInit->pEEPROMCurPtr = uAddr;
1374 pHwInit->uEEPROMCurLen-= uDeltaLength;
1377 TRACE2(pHwInit->hReport, REPORT_SEVERITY_INIT , "NVS::WriteTLV: pEEPROMCurPtr= %x, Length=%d\n", pHwInit->pEEPROMCurPtr, pHwInit->uEEPROMCurLen);
1379 if (pHwInit->uEEPROMCurLen)
1382 pHwInit->uSavedDataForWspiHdr = *(TI_UINT32 *)(pHwInit->pEEPROMCurPtr - WSPI_PAD_LEN_WRITE);
1385 HW_INIT_PTXN_SET(pHwInit, pTxn)
1387 BUILD_TTxnStruct(pTxn, CMD_MBOX_ADDRESS, pHwInit->pEEPROMCurPtr, pHwInit->uEEPROMCurLen,
1391 status = twIf_Transact(pHwInit->hTwIf, pTxn);
1393 pHwInit->uEEPROMCurLen = 0;
1394 pHwInit->uNVSStatus = status;
1396 EXCEPT (pHwInit, status);
1401 *(TI_UINT32 *)(pHwInit->pEEPROMCurPtr - WSPI_PAD_LEN_WRITE) = pHwInit->uSavedDataForWspiHdr;
1404 if (pHwInit->uEEPROMStatus == TXN_STATUS_PENDING ||
1405 pHwInit->uNVSStatus == TXN_STATUS_PENDING)
1434 THwInit *pHwInit = (THwInit *)hHwInit;
1440 pHwInit->uTxnIndex = 0;
1444 switch (pHwInit->uLoadStage)
1447 pHwInit->uLoadStage = 1;
1450 if ((pHwInit->uFwLength % ADDRESS_SIZE) != 0)
1452 TRACE1(pHwInit->hReport, REPORT_SEVERITY_ERROR , "Length of downloaded Portion (%d) is not aligned\n",pHwInit->uFwLength);
1453 EXCEPT_L (pHwInit, TXN_STATUS_ERROR);
1456 TRACE2(pHwInit->hReport, REPORT_SEVERITY_INIT , "Image addr=0x%x, Len=0x%x\n", pHwInit->pFwBuf, pHwInit->uFwLength);
1459 SET_FW_LOAD_PARTITION(pHwInit->aPartition,pHwInit->uFwAddress)
1460 hwInit_SetPartition (pHwInit,pHwInit->aPartition);
1466 pHwInit->uLoadStage = 2;
1468 if (pHwInit->uFwLength < MAX_SDIO_BLOCK)
1470 pHwInit->uLoadStage = 4;
1473 pHwInit->uBlockReadNum = 0;
1474 pHwInit->uBlockWriteNum = 0;
1475 pHwInit->uPartitionLimit = pHwInit->uFwAddress + uMaxPartitionSize;
1482 if (pHwInit->uBlockReadNum < (pHwInit->uFwLength / MAX_SDIO_BLOCK))
1484 pHwInit->uLoadStage = 3;
1488 if ( ((pHwInit->uBlockWriteNum + 2) * MAX_SDIO_BLOCK + pHwInit->uFwAddress) > pHwInit->uPartitionLimit)
1490 pHwInit->uFwAddress += pHwInit->uBlockWriteNum * MAX_SDIO_BLOCK;
1492 pHwInit->uPartitionLimit = pHwInit->uFwAddress + uMaxPartitionSize;
1494 SET_FW_LOAD_PARTITION(pHwInit->aPartition,pHwInit->uFwAddress)
1495 hwInit_SetPartition (pHwInit,pHwInit->aPartition);
1497 pHwInit->uBlockWriteNum = 0;
1498 TRACE1(pHwInit->hReport, REPORT_SEVERITY_INIT , "Change partition to address offset = 0x%x\n", pHwInit->uFwAddress + pHwInit->uBlockWriteNum * MAX_SDIO_BLOCK);
1499 EXCEPT_L (pHwInit, TxnStatus);
1504 pHwInit->uLoadStage = 4;
1505 TRACE0(pHwInit->hReport, REPORT_SEVERITY_INIT , "Load firmware with Portions\n");
1510 pHwInit->uLoadStage = 2;
1512 pHwInit->uTxnIndex = 0;
1515 os_memoryCopy (pHwInit->hOs,
1516 (void *)&pHwInit->auFwTmpBuf[WSPI_PAD_LEN_WRITE],
1517 (void *)(pHwInit->pFwBuf + pHwInit->uBlockReadNum * MAX_SDIO_BLOCK),
1521 BUILD_HW_INIT_FW_DL_TXN(pHwInit, pTxn, (pHwInit->uFwAddress + pHwInit->uBlockWriteNum * MAX_SDIO_BLOCK),
1522 (pHwInit->auFwTmpBuf + WSPI_PAD_LEN_WRITE), MAX_SDIO_BLOCK, TXN_DIRECTION_WRITE,
1524 TxnStatus = twIf_Transact(pHwInit->hTwIf, pTxn);
1529 TRACE1(pHwInit->hReport, REPORT_SEVERITY_ERROR , "hwInit_LoadFwImageSm: twIf_Transact retruned status=0x%x\n", TxnStatus);
1532 pHwInit->uBlockWriteNum ++;
1533 pHwInit->uBlockReadNum ++;
1534 EXCEPT_L (pHwInit, TxnStatus);
1538 pHwInit->uLoadStage = 5;
1540 pHwInit->uTxnIndex = 0;
1543 if ( pHwInit->uFwLength % MAX_SDIO_BLOCK == 0 )
1550 os_memoryCopy (pHwInit->hOs,
1551 (void *)&pHwInit->auFwTmpBuf[WSPI_PAD_LEN_WRITE],
1552 (void *)(pHwInit->pFwBuf + pHwInit->uBlockReadNum * MAX_SDIO_BLOCK),
1553 pHwInit->uFwLength % MAX_SDIO_BLOCK);
1556 BUILD_HW_INIT_FW_DL_TXN(pHwInit, pTxn, (pHwInit->uFwAddress + pHwInit->uBlockWriteNum * MAX_SDIO_BLOCK),
1557 (pHwInit->auFwTmpBuf + WSPI_PAD_LEN_WRITE), (pHwInit->uFwLength % MAX_SDIO_BLOCK), TXN_DIRECTION_WRITE,
1559 TxnStatus = twIf_Transact(pHwInit->hTwIf, pTxn);
1563 TRACE1(pHwInit->hReport, REPORT_SEVERITY_ERROR , "hwInit_LoadFwImageSm: last block retruned status=0x%x\n", TxnStatus);
1566 EXCEPT_L (pHwInit, TxnStatus);
1570 pHwInit->uLoadStage = 0;
1573 if ( pHwInit->bFwBufLast == TI_TRUE )
1583 if ( pHwInit->fFinalizeDownload != NULL )
1585 (pHwInit->fFinalizeDownload) (pHwInit->hFinalizeDownload);
1612 THwInit *pHwInit = (THwInit *)hHwInit;
1613 TTwd *pTWD = (TTwd *)pHwInit->hTWD;
1624 switch (pHwInit->uRegStage)
1627 pHwInit->uRegStage = 1;
1628 pHwInit->uTxnIndex++;
1633 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, GPIO_SELECT, 0,
1635 status = twIf_Transact(pHwInit->hTwIf, pTxn);
1637 EXCEPT (pHwInit, status)
1640 pHwInit->uRegStage ++;
1641 pHwInit->uRegLoop = 0;
1643 /* We don't zero pHwInit->uTxnIndex at the begining because we need it's value to the next transaction */
1644 val = (pHwInit->aHwInitTxn[pHwInit->uTxnIndex].uData);
1647 pHwInit->uTxnIndex = 0;
1649 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, GPIO_SELECT, val,
1652 twIf_Transact(pHwInit->hTwIf, pTxn);
1654 pHwInit->uTxnIndex++;
1656 pHwInit->uRegData = FUNC7_SEL;
1662 pHwInit->uRegStage ++;
1663 add = pHwInit->uRegData;
1671 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, OCP_POR_CTR, val,
1673 twIf_Transact(pHwInit->hTwIf, pTxn);
1675 pHwInit->uTxnIndex++;
1677 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, OCP_CMD, 0x2,
1679 twIf_Transact(pHwInit->hTwIf, pTxn);
1685 pHwInit->uRegStage ++;
1686 pHwInit->uTxnIndex++;
1688 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, OCP_DATA_RD, 0,
1690 status = twIf_Transact(pHwInit->hTwIf, pTxn);
1692 EXCEPT (pHwInit, status)
1697 val = (pHwInit->aHwInitTxn[pHwInit->uTxnIndex].uData);
1699 pHwInit->uTxnIndex = 0;
1704 pHwInit->uRegStage ++;
1705 pHwInit->uRegLoop = 0;
1710 TRACE0(pHwInit->hReport, REPORT_SEVERITY_ERROR , "can't writing bt_func7_sel\n");
1712 TWD_FinalizeFEMRead(pHwInit->hTWD);
1719 if (pHwInit->uRegLoop < READ_TOP_REG_LOOP)
1721 pHwInit->uRegStage = 3;
1722 pHwInit->uRegLoop++;
1727 TRACE0(pHwInit->hReport, REPORT_SEVERITY_ERROR , "Timeout waiting for writing bt_func7_sel\n");
1729 TWD_FinalizeFEMRead(pHwInit->hTWD);
1739 pHwInit->uRegStage ++;
1740 add = pHwInit->uRegData;
1745 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, OCP_POR_CTR, value,
1747 twIf_Transact(pHwInit->hTwIf, pTxn);
1749 pHwInit->uTxnIndex++;
1751 if (pHwInit->uRegSeqStage == 0)
1753 if (pHwInit->uRegData == FUNC7_SEL)
1760 if (pHwInit->uRegData == FUNC7_SEL)
1769 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, OCP_POR_WDATA, value,
1771 twIf_Transact(pHwInit->hTwIf, pTxn);
1773 pHwInit->uTxnIndex++;
1775 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, OCP_CMD, 0x1,
1778 /*BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, INDIRECT_REG5, 0x1,
1781 status = twIf_Transact(pHwInit->hTwIf, pTxn);
1783 pHwInit->uTxnIndex++;
1785 if ((pHwInit->uRegData == FUNC7_SEL)&& (pHwInit->uRegSeqStage == 0))
1787 pHwInit->uRegData = FUNC7_PULL;
1788 pHwInit->uRegStage = 2;
1792 if ((pHwInit->uRegData == FUNC7_PULL)&& (pHwInit->uRegSeqStage == 1))
1794 pHwInit->uRegData = FUNC7_SEL;
1795 pHwInit->uRegStage = 2;
1799 EXCEPT (pHwInit, status)
1804 if (pHwInit->uRegSeqStage == 1)
1806 pHwInit->uRegStage = 8;
1810 pHwInit->uRegStage ++;
1811 pHwInit->uTxnIndex++;
1813 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, GPIO_OE_RADIO, 0,
1815 status = twIf_Transact(pHwInit->hTwIf, pTxn);
1816 EXCEPT (pHwInit, status)
1821 pHwInit->uRegStage ++;
1823 /* We don't zero pHwInit->uTxnIndex at the begining because we need it's value to the next transaction */
1824 val = (pHwInit->aHwInitTxn[pHwInit->uTxnIndex].uData);
1827 pHwInit->uTxnIndex = 0;
1828 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, GPIO_OE_RADIO, val,
1830 twIf_Transact(pHwInit->hTwIf, pTxn);
1832 pHwInit->uTxnIndex++;
1834 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, GPIO_IN, 0,
1836 status = twIf_Transact(pHwInit->hTwIf, pTxn);
1838 EXCEPT (pHwInit, status)
1842 if (pHwInit->uRegSeqStage == 0)
1844 val = (pHwInit->aHwInitTxn[pHwInit->uTxnIndex].uData);
1855 pHwInit->uTxnIndex = 0;
1856 pHwInit->uRegSeqStage = 1;
1857 pHwInit->uRegStage = 2;
1858 pHwInit->uRegData = FUNC7_PULL;
1863 TRACE0(pHwInit->hReport, REPORT_SEVERITY_INFORMATION, "hwInit_ReadRadioParamsSm Ended Successfully\n");
1865 TWD_FinalizeFEMRead(pHwInit->hTWD);
1887 THwInit *pHwInit = (THwInit *)hHwInit;
1889 pHwInit->uRegStage = 0;
1890 pHwInit->uRegSeqStage = 0;
1904 THwInit *pHwInit = (THwInit *)hHwInit;
1906 pHwInit->uRegStage = 0;
1907 pHwInit->uRegSeqStage = 0;
1926 THwInit *pHwInit = (THwInit *)hHwInit;
1953 switch (pHwInit->uRegStage)
1957 pHwInit->uRegStage = 1;
1958 pHwInit->uTxnIndex++;
1959 pHwInit->uRegLoop = 0;
1967 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, OCP_POR_CTR, val,
1970 twIf_Transact(pHwInit->hTwIf, pTxn);
1972 pHwInit->uTxnIndex++;
1976 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, OCP_CMD, 0x2,
1978 twIf_Transact(pHwInit->hTwIf, pTxn);
1984 pHwInit->uRegStage ++;
1985 pHwInit->uTxnIndex++;
1987 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, OCP_DATA_RD, 0,
1989 status = twIf_Transact(pHwInit->hTwIf, pTxn);
1991 EXCEPT (pHwInit, status)
1996 val = pHwInit->aHwInitTxn[pHwInit->uTxnIndex].uData;
1998 pHwInit->uTxnIndex = 0;
2005 pHwInit->uRegStage ++;
2006 pHwInit->uRegLoop = 0;
2011 TRACE0(pHwInit->hReport, REPORT_SEVERITY_ERROR , "can't writing bt_func7_sel\n");
2012 TWD_FinalizePolarityRead(pHwInit->hTWD);
2019 if (pHwInit->uRegLoop < READ_TOP_REG_LOOP)
2021 pHwInit->uRegStage = 1;
2022 pHwInit->uRegLoop++;
2027 TRACE0(pHwInit->hReport, REPORT_SEVERITY_ERROR , "Timeout waiting for writing bt_func7_sel\n");
2028 TWD_FinalizePolarityRead(pHwInit->hTWD);
2040 pHwInit->uRegStage ++;
2047 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, OCP_POR_CTR, value,
2050 twIf_Transact(pHwInit->hTwIf, pTxn);
2052 pHwInit->uTxnIndex++;
2055 TRACE0(pHwInit->hReport, REPORT_SEVERITY_INFORMATION , "Hwinit IRQ polarity active high\n");
2059 TRACE0(pHwInit->hReport, REPORT_SEVERITY_INFORMATION , "Hwinit IRQ polarity active low\n");
2064 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, OCP_POR_WDATA, val,
2066 twIf_Transact(pHwInit->hTwIf, pTxn);
2068 pHwInit->uTxnIndex++;
2071 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, OCP_CMD, 0x1,
2073 status = twIf_Transact(pHwInit->hTwIf, pTxn);
2075 pHwInit->uTxnIndex++;
2077 EXCEPT (pHwInit, status)
2082 TWD_FinalizePolarityRead(pHwInit->hTWD);
2103 THwInit *pHwInit = (THwInit *)hHwInit;
2105 pHwInit->uTopStage = 0;
2109 pHwInit->uTopRegAddr = uAddress;
2110 pHwInit->uTopRegValue = uValue & 0xffff;
2133 THwInit *pHwInit = (THwInit *)hHwInit;
2139 switch (pHwInit->uTopStage)
2142 pHwInit->uTopStage = 1;
2144 pHwInit->uTxnIndex++;
2146 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, OCP_POR_CTR, pHwInit->uTopRegAddr,
2148 twIf_Transact(pHwInit->hTwIf, pTxn);
2150 pHwInit->uTxnIndex++;
2152 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, OCP_POR_WDATA, pHwInit->uTopRegValue,
2154 twIf_Transact(pHwInit->hTwIf, pTxn);
2156 pHwInit->uTxnIndex++;
2158 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, OCP_CMD, 0x1,
2160 status = twIf_Transact(pHwInit->hTwIf, pTxn);
2162 pHwInit->uTxnIndex++;
2164 EXCEPT (pHwInit, status)
2169 pHwInit->uTxnIndex = 0;
2189 THwInit *pHwInit = (THwInit *)hHwInit;
2191 pHwInit->uTopStage = 0;
2195 pHwInit->uTopRegAddr = uAddress;
2226 THwInit *pHwInit = (THwInit *)hHwInit;
2232 switch (pHwInit->uTopStage)
2235 pHwInit->uTopStage = 1;
2236 pHwInit->uTxnIndex++;
2237 pHwInit->uRegLoop = 0;
2240 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, OCP_POR_CTR, pHwInit->uTopRegAddr,
2242 twIf_Transact(pHwInit->hTwIf, pTxn);
2244 pHwInit->uTxnIndex++;
2245 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, OCP_CMD, 0x2,
2247 twIf_Transact(pHwInit->hTwIf, pTxn);
2252 pHwInit->uTopStage ++;
2253 pHwInit->uTxnIndex++;
2255 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, OCP_DATA_RD, 0,
2257 status = twIf_Transact(pHwInit->hTwIf, pTxn);
2259 EXCEPT (pHwInit, status)
2263 pHwInit->uTopRegValue = pHwInit->aHwInitTxn[pHwInit->uTxnIndex].uData;
2265 pHwInit->uTxnIndex = 0;
2268 if (pHwInit->uTopRegValue & BIT_18)
2270 if ((pHwInit->uTopRegValue & BIT_16) && (!(pHwInit->uTopRegValue & BIT_17)))
2272 pHwInit->uTopRegValue &= 0xffff;
2273 pHwInit->uTxnIndex = 0;
2274 pHwInit->uRegLoop = 0;
2279 TRACE0(pHwInit->hReport, REPORT_SEVERITY_ERROR , "can't writing bt_func7_sel\n");
2285 if (pHwInit->uRegLoop < READ_TOP_REG_LOOP)
2287 pHwInit->uTopStage = 1;
2288 pHwInit->uRegLoop++;
2292 TRACE0(pHwInit->hReport, REPORT_SEVERITY_ERROR , "Timeout waiting for writing bt_func7_sel\n");
