Lines Matching refs:pTxn
152 #define HW_INIT_PTXN_SET(pHwInit, pTxn) pTxn = (TTxnStruct*)&(pHwInit->aHwInitTxn[pHwInit->uTxnIndex].tTxnStruct);
154 #define BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, uAddr, uVal, uSize, direction, fCB, hCB) \
155 HW_INIT_PTXN_SET(pHwInit, pTxn) \
156 TXN_PARAM_SET_DIRECTION(pTxn, direction); \
158 BUILD_TTxnStruct(pTxn, uAddr, &(pHwInit->aHwInitTxn[pHwInit->uTxnIndex].uData), uSize, fCB, hCB)
160 #define BUILD_HW_INIT_FW_STATIC_TXN(pHwInit, pTxn, uAddr, fCB, hCB) \
161 HW_INIT_PTXN_SET(pHwInit, pTxn) \
162 TXN_PARAM_SET_DIRECTION(pTxn, TXN_DIRECTION_READ); \
163 BUILD_TTxnStruct(pTxn, uAddr, &(pHwInit->tFwStaticTxn.tFwStaticInfo), sizeof(FwStaticData_t), fCB, hCB)
165 #define BUILD_HW_INIT_FW_DL_TXN(pHwInit, pTxn, uAddr, uVal, uSize, direction, fCB, hCB) \
166 HW_INIT_PTXN_SET(pHwInit, pTxn) \
167 TXN_PARAM_SET_DIRECTION(pTxn, direction); \
168 BUILD_TTxnStruct(pTxn, uAddr, uVal, uSize, fCB, hCB)
456 TTxnStruct* pTxn;
482 HW_INIT_PTXN_SET(pHwInit, pTxn)
484 TXN_PARAM_SET(pTxn, TXN_LOW_PRIORITY, TXN_FUNC_ID_WLAN, TXN_DIRECTION_WRITE, TXN_INC_ADDR)
612 TTxnStruct *pTxn;
630 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, SCR_PAD8, 0xBABABABE,
632 twIf_Transact(pHwInit->hTwIf, pTxn);
649 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, PLL_PARAMETERS, clkVal,
651 twIf_Transact(pHwInit->hTwIf, pTxn);
656 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, PLL_PARAMETERS, 0,
658 status = twIf_Transact(pHwInit->hTwIf, pTxn);
673 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, WU_COUNTER_PAUSE, uData,
675 twIf_Transact(pHwInit->hTwIf, pTxn);
680 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL,
682 twIf_Transact(pHwInit->hTwIf, pTxn);
695 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, DRPW_SCRATCH_START, 0,
697 status = twIf_Transact(pHwInit->hTwIf, pTxn);
709 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, DRPW_SCRATCH_START, clkVal,
711 twIf_Transact(pHwInit->hTwIf, pTxn);
725 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, ACX_REG_INTERRUPT_MASK, ACX_INTR_ALL,
727 twIf_Transact(pHwInit->hTwIf, pTxn);
732 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, CHIP_ID, 0,
734 status = twIf_Transact(pHwInit->hTwIf, pTxn);
818 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, ACX_EEPROMLESS_IND_REG, ACX_EEPROMLESS_IND_REG,
820 twIf_Transact(pHwInit->hTwIf, pTxn);
831 TXN_PARAM_SET(pTxn, TXN_LOW_PRIORITY, TXN_FUNC_ID_WLAN, TXN_DIRECTION_WRITE, TXN_INC_ADDR)
832 BUILD_TTxnStruct(pTxn, ACX_REG_EE_START, &pHwInit->uRegister, REGISTER_SIZE, 0, NULL, NULL)
833 twIf_Transact(pHwInit->hTwIf, pTxn);*/
840 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, ACX_EEPROMLESS_IND_REG, USE_EEPROM,
842 twIf_Transact(pHwInit->hTwIf, pTxn);
850 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, CHIP_ID, 0,
852 status = twIf_Transact(pHwInit->hTwIf, pTxn);
875 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, SCR_PAD2, 0,
877 status = twIf_Transact(pHwInit->hTwIf, pTxn);
1021 TTxnStruct* pTxn;
1039 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, ACX_REG_ECPU_CONTROL, 0,
1041 status = twIf_Transact(pHwInit->hTwIf, pTxn);
1055 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, ACX_REG_ECPU_CONTROL, (pHwInit->uFinData | ECPU_CONTROL_HALT),
1057 twIf_Transact(pHwInit->hTwIf, pTxn);
1067 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, CHIP_ID, 0,
1069 status = twIf_Transact(pHwInit->hTwIf, pTxn);
1097 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, ACX_REG_INTERRUPT_NO_CLEAR, 0,
1099 status = twIf_Transact(pHwInit->hTwIf, pTxn);
1128 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, ACX_REG_INTERRUPT_ACK, ACX_INTR_INIT_COMPLETE,
1130 twIf_Transact(pHwInit->hTwIf, pTxn);
1189 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, ACX_REG_INTERRUPT_MASK, (~uIntVect),
1191 twIf_Transact(pHwInit->hTwIf, pTxn);
1195 BUILD_HW_INIT_FW_STATIC_TXN(pHwInit, pTxn, cmdMbox_GetMboxAddress (pTWD->hCmdMbox),
1197 status = twIf_Transact(pHwInit->hTwIf, pTxn);
1235 TTxnStruct* pTxn;
1240 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, REG_ENABLE_TX_RX, 0x0,
1242 twIf_Transact(pHwInit->hTwIf, pTxn);
1247 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, SPARE_A2, 0xFFFF,
1249 status = twIf_Transact(pHwInit->hTwIf, pTxn);
1272 TTxnStruct* pTxn;
1333 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, (REGISTERS_BASE+pHwInit->uEEPROMRegAddr), val,
1335 status = twIf_Transact(pHwInit->hTwIf, pTxn);
1385 HW_INIT_PTXN_SET(pHwInit, pTxn)
1386 TXN_PARAM_SET_DIRECTION(pTxn, TXN_DIRECTION_WRITE);
1387 BUILD_TTxnStruct(pTxn, CMD_MBOX_ADDRESS, pHwInit->pEEPROMCurPtr, pHwInit->uEEPROMCurLen,
1391 status = twIf_Transact(pHwInit->hTwIf, pTxn);
1438 TTxnStruct* pTxn;
1521 BUILD_HW_INIT_FW_DL_TXN(pHwInit, pTxn, (pHwInit->uFwAddress + pHwInit->uBlockWriteNum * MAX_SDIO_BLOCK),
1524 TxnStatus = twIf_Transact(pHwInit->hTwIf, pTxn);
1556 BUILD_HW_INIT_FW_DL_TXN(pHwInit, pTxn, (pHwInit->uFwAddress + pHwInit->uBlockWriteNum * MAX_SDIO_BLOCK),
1559 TxnStatus = twIf_Transact(pHwInit->hTwIf, pTxn);
1618 TTxnStruct *pTxn;
1633 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, GPIO_SELECT, 0,
1635 status = twIf_Transact(pHwInit->hTwIf, pTxn);
1649 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, GPIO_SELECT, val,
1652 twIf_Transact(pHwInit->hTwIf, pTxn);
1671 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, OCP_POR_CTR, val,
1673 twIf_Transact(pHwInit->hTwIf, pTxn);
1677 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, OCP_CMD, 0x2,
1679 twIf_Transact(pHwInit->hTwIf, pTxn);
1688 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, OCP_DATA_RD, 0,
1690 status = twIf_Transact(pHwInit->hTwIf, pTxn);
1745 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, OCP_POR_CTR, value,
1747 twIf_Transact(pHwInit->hTwIf, pTxn);
1769 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, OCP_POR_WDATA, value,
1771 twIf_Transact(pHwInit->hTwIf, pTxn);
1775 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, OCP_CMD, 0x1,
1778 /*BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, INDIRECT_REG5, 0x1,
1781 status = twIf_Transact(pHwInit->hTwIf, pTxn);
1813 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, GPIO_OE_RADIO, 0,
1815 status = twIf_Transact(pHwInit->hTwIf, pTxn);
1828 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, GPIO_OE_RADIO, val,
1830 twIf_Transact(pHwInit->hTwIf, pTxn);
1834 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, GPIO_IN, 0,
1836 status = twIf_Transact(pHwInit->hTwIf, pTxn);
1929 TTxnStruct *pTxn;
1967 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, OCP_POR_CTR, val,
1970 twIf_Transact(pHwInit->hTwIf, pTxn);
1976 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, OCP_CMD, 0x2,
1978 twIf_Transact(pHwInit->hTwIf, pTxn);
1987 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, OCP_DATA_RD, 0,
1989 status = twIf_Transact(pHwInit->hTwIf, pTxn);
2047 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, OCP_POR_CTR, value,
2050 twIf_Transact(pHwInit->hTwIf, pTxn);
2064 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, OCP_POR_WDATA, val,
2066 twIf_Transact(pHwInit->hTwIf, pTxn);
2071 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, OCP_CMD, 0x1,
2073 status = twIf_Transact(pHwInit->hTwIf, pTxn);
2134 TTxnStruct *pTxn;
2146 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, OCP_POR_CTR, pHwInit->uTopRegAddr,
2148 twIf_Transact(pHwInit->hTwIf, pTxn);
2152 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, OCP_POR_WDATA, pHwInit->uTopRegValue,
2154 twIf_Transact(pHwInit->hTwIf, pTxn);
2158 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, OCP_CMD, 0x1,
2160 status = twIf_Transact(pHwInit->hTwIf, pTxn);
2227 TTxnStruct *pTxn;
2240 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, OCP_POR_CTR, pHwInit->uTopRegAddr,
2242 twIf_Transact(pHwInit->hTwIf, pTxn);
2245 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, OCP_CMD, 0x2,
2247 twIf_Transact(pHwInit->hTwIf, pTxn);
2255 BUILD_HW_INIT_TXN_DATA(pHwInit, pTxn, OCP_DATA_RD, 0,
2257 status = twIf_Transact(pHwInit->hTwIf, pTxn);
