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      1 /*
      2  * Broadcom SDIO/PCMCIA
      3  * Software-specific definitions shared between device and host side
      4  *
      5  * Copyright (C) 1999-2010, Broadcom Corporation
      6  *
      7  *      Unless you and Broadcom execute a separate written software license
      8  * agreement governing use of this software, this software is licensed to you
      9  * under the terms of the GNU General Public License version 2 (the "GPL"),
     10  * available at http://www.broadcom.com/licenses/GPLv2.php, with the
     11  * following added to such license:
     12  *
     13  *      As a special exception, the copyright holders of this software give you
     14  * permission to link this software with independent modules, and to copy and
     15  * distribute the resulting executable under terms of your choice, provided that
     16  * you also meet, for each linked independent module, the terms and conditions of
     17  * the license of that module.  An independent module is a module which is not
     18  * derived from this software.  The special exception does not apply to any
     19  * modifications of the software.
     20  *
     21  *      Notwithstanding the above, under no circumstances may you combine this
     22  * software in any way with any other Broadcom software provided under a license
     23  * other than the GPL, without Broadcom's express prior written consent.
     24  *
     25  * $Id: bcmsdpcm.h,v 1.1.2.4 2010/07/02 01:15:46 Exp $
     26  */
     27 
     28 #ifndef	_bcmsdpcm_h_
     29 #define	_bcmsdpcm_h_
     30 
     31 /*
     32  * Software allocation of To SB Mailbox resources
     33  */
     34 
     35 /* intstatus bits */
     36 #define I_SMB_NAK	I_SMB_SW0	/* To SB Mailbox Frame NAK */
     37 #define I_SMB_INT_ACK	I_SMB_SW1	/* To SB Mailbox Host Interrupt ACK */
     38 #define I_SMB_USE_OOB	I_SMB_SW2	/* To SB Mailbox Use OOB Wakeup */
     39 #define I_SMB_DEV_INT	I_SMB_SW3	/* To SB Mailbox Miscellaneous Interrupt */
     40 
     41 /* tosbmailbox bits corresponding to intstatus bits */
     42 #define SMB_NAK		(1 << 0)	/* To SB Mailbox Frame NAK */
     43 #define SMB_INT_ACK	(1 << 1)	/* To SB Mailbox Host Interrupt ACK */
     44 #define SMB_USE_OOB	(1 << 2)	/* To SB Mailbox Use OOB Wakeup */
     45 #define SMB_DEV_INT	(1 << 3)	/* To SB Mailbox Miscellaneous Interrupt */
     46 #define SMB_MASK	0x0000000f	/* To SB Mailbox Mask */
     47 
     48 /* tosbmailboxdata */
     49 #define SMB_DATA_VERSION_MASK	0x00ff0000	/* host protocol version (sent with F2 enable) */
     50 #define SMB_DATA_VERSION_SHIFT	16		/* host protocol version (sent with F2 enable) */
     51 
     52 /*
     53  * Software allocation of To Host Mailbox resources
     54  */
     55 
     56 /* intstatus bits */
     57 #define I_HMB_FC_STATE	I_HMB_SW0	/* To Host Mailbox Flow Control State */
     58 #define I_HMB_FC_CHANGE	I_HMB_SW1	/* To Host Mailbox Flow Control State Changed */
     59 #define I_HMB_FRAME_IND	I_HMB_SW2	/* To Host Mailbox Frame Indication */
     60 #define I_HMB_HOST_INT	I_HMB_SW3	/* To Host Mailbox Miscellaneous Interrupt */
     61 
     62 /* tohostmailbox bits corresponding to intstatus bits */
     63 #define HMB_FC_ON	(1 << 0)	/* To Host Mailbox Flow Control State */
     64 #define HMB_FC_CHANGE	(1 << 1)	/* To Host Mailbox Flow Control State Changed */
     65 #define HMB_FRAME_IND	(1 << 2)	/* To Host Mailbox Frame Indication */
     66 #define HMB_HOST_INT	(1 << 3)	/* To Host Mailbox Miscellaneous Interrupt */
     67 #define HMB_MASK	0x0000000f	/* To Host Mailbox Mask */
     68 
     69 /* tohostmailboxdata */
     70 #define HMB_DATA_NAKHANDLED	1	/* we're ready to retransmit NAK'd frame to host */
     71 #define HMB_DATA_DEVREADY	2	/* we're ready to to talk to host after enable */
     72 #define HMB_DATA_FC		4	/* per prio flowcontrol update flag to host */
     73 #define HMB_DATA_FWREADY	8	/* firmware is ready for protocol activity */
     74 
     75 #define HMB_DATA_FCDATA_MASK	0xff000000	/* per prio flowcontrol data */
     76 #define HMB_DATA_FCDATA_SHIFT	24		/* per prio flowcontrol data */
     77 
     78 #define HMB_DATA_VERSION_MASK	0x00ff0000	/* device protocol version (with devready) */
     79 #define HMB_DATA_VERSION_SHIFT	16		/* device protocol version (with devready) */
     80 
     81 /*
     82  * Software-defined protocol header
     83  */
     84 
     85 /* Current protocol version */
     86 #define SDPCM_PROT_VERSION	4
     87 
     88 /* SW frame header */
     89 #define SDPCM_SEQUENCE_MASK		0x000000ff	/* Sequence Number Mask */
     90 #define SDPCM_PACKET_SEQUENCE(p) (((uint8 *)p)[0] & 0xff) /* p starts w/SW Header */
     91 
     92 #define SDPCM_CHANNEL_MASK		0x00000f00	/* Channel Number Mask */
     93 #define SDPCM_CHANNEL_SHIFT		8		/* Channel Number Shift */
     94 #define SDPCM_PACKET_CHANNEL(p) (((uint8 *)p)[1] & 0x0f) /* p starts w/SW Header */
     95 
     96 #define SDPCM_FLAGS_MASK		0x0000f000	/* Mask of flag bits */
     97 #define SDPCM_FLAGS_SHIFT		12		/* Flag bits shift */
     98 #define SDPCM_PACKET_FLAGS(p) ((((uint8 *)p)[1] & 0xf0) >> 4) /* p starts w/SW Header */
     99 
    100 /* Next Read Len: lookahead length of next frame, in 16-byte units (rounded up) */
    101 #define SDPCM_NEXTLEN_MASK		0x00ff0000	/* Next Read Len Mask */
    102 #define SDPCM_NEXTLEN_SHIFT		16		/* Next Read Len Shift */
    103 #define SDPCM_NEXTLEN_VALUE(p) ((((uint8 *)p)[2] & 0xff) << 4) /* p starts w/SW Header */
    104 #define SDPCM_NEXTLEN_OFFSET		2
    105 
    106 /* Data Offset from SOF (HW Tag, SW Tag, Pad) */
    107 #define SDPCM_DOFFSET_OFFSET		3		/* Data Offset */
    108 #define SDPCM_DOFFSET_VALUE(p) 		(((uint8 *)p)[SDPCM_DOFFSET_OFFSET] & 0xff)
    109 #define SDPCM_DOFFSET_MASK		0xff000000
    110 #define SDPCM_DOFFSET_SHIFT		24
    111 
    112 #define SDPCM_FCMASK_OFFSET		4		/* Flow control */
    113 #define SDPCM_FCMASK_VALUE(p)		(((uint8 *)p)[SDPCM_FCMASK_OFFSET ] & 0xff)
    114 #define SDPCM_WINDOW_OFFSET		5		/* Credit based fc */
    115 #define SDPCM_WINDOW_VALUE(p)		(((uint8 *)p)[SDPCM_WINDOW_OFFSET] & 0xff)
    116 #define SDPCM_VERSION_OFFSET		6		/* Version # */
    117 #define SDPCM_VERSION_VALUE(p)		(((uint8 *)p)[SDPCM_VERSION_OFFSET] & 0xff)
    118 #define SDPCM_UNUSED_OFFSET		7		/* Spare */
    119 #define SDPCM_UNUSED_VALUE(p)		(((uint8 *)p)[SDPCM_UNUSED_OFFSET] & 0xff)
    120 
    121 #define SDPCM_SWHEADER_LEN	8	/* SW header is 64 bits */
    122 
    123 /* logical channel numbers */
    124 #define SDPCM_CONTROL_CHANNEL	0	/* Control Request/Response Channel Id */
    125 #define SDPCM_EVENT_CHANNEL	1	/* Asyc Event Indication Channel Id */
    126 #define SDPCM_DATA_CHANNEL	2	/* Data Xmit/Recv Channel Id */
    127 #define SDPCM_GLOM_CHANNEL	3	/* For coalesced packets (superframes) */
    128 #define SDPCM_TEST_CHANNEL	15	/* Reserved for test/debug packets */
    129 #define SDPCM_MAX_CHANNEL	15
    130 
    131 #define SDPCM_SEQUENCE_WRAP	256	/* wrap-around val for eight-bit frame seq number */
    132 
    133 #define SDPCM_FLAG_RESVD0	0x01
    134 #define SDPCM_FLAG_RESVD1	0x02
    135 #define SDPCM_FLAG_GSPI_TXENAB	0x04
    136 #define SDPCM_FLAG_GLOMDESC	0x08	/* Superframe descriptor mask */
    137 
    138 /* For GLOM_CHANNEL frames, use a flag to indicate descriptor frame */
    139 #define SDPCM_GLOMDESC_FLAG	(SDPCM_FLAG_GLOMDESC << SDPCM_FLAGS_SHIFT)
    140 
    141 #define SDPCM_GLOMDESC(p)	(((uint8 *)p)[1] & 0x80)
    142 
    143 /* For TEST_CHANNEL packets, define another 4-byte header */
    144 #define SDPCM_TEST_HDRLEN	4	/* Generally: Cmd(1), Ext(1), Len(2);
    145 					 * Semantics of Ext byte depend on command.
    146 					 * Len is current or requested frame length, not
    147 					 * including test header; sent little-endian.
    148 					 */
    149 #define SDPCM_TEST_DISCARD	0x01	/* Receiver discards. Ext is a pattern id. */
    150 #define SDPCM_TEST_ECHOREQ	0x02	/* Echo request. Ext is a pattern id. */
    151 #define SDPCM_TEST_ECHORSP	0x03	/* Echo response. Ext is a pattern id. */
    152 #define SDPCM_TEST_BURST	0x04	/* Receiver to send a burst. Ext is a frame count */
    153 #define SDPCM_TEST_SEND		0x05	/* Receiver sets send mode. Ext is boolean on/off */
    154 
    155 /* Handy macro for filling in datagen packets with a pattern */
    156 #define SDPCM_TEST_FILL(byteno, id)	((uint8)(id + byteno))
    157 
    158 /*
    159  * Software counters (first part matches hardware counters)
    160  */
    161 
    162 typedef volatile struct {
    163 	uint32 cmd52rd;		/* Cmd52RdCount, SDIO: cmd52 reads */
    164 	uint32 cmd52wr;		/* Cmd52WrCount, SDIO: cmd52 writes */
    165 	uint32 cmd53rd;		/* Cmd53RdCount, SDIO: cmd53 reads */
    166 	uint32 cmd53wr;		/* Cmd53WrCount, SDIO: cmd53 writes */
    167 	uint32 abort;		/* AbortCount, SDIO: aborts */
    168 	uint32 datacrcerror;	/* DataCrcErrorCount, SDIO: frames w/CRC error */
    169 	uint32 rdoutofsync;	/* RdOutOfSyncCount, SDIO/PCMCIA: Rd Frm out of sync */
    170 	uint32 wroutofsync;	/* RdOutOfSyncCount, SDIO/PCMCIA: Wr Frm out of sync */
    171 	uint32 writebusy;	/* WriteBusyCount, SDIO: device asserted "busy" */
    172 	uint32 readwait;	/* ReadWaitCount, SDIO: no data ready for a read cmd */
    173 	uint32 readterm;	/* ReadTermCount, SDIO: read frame termination cmds */
    174 	uint32 writeterm;	/* WriteTermCount, SDIO: write frames termination cmds */
    175 	uint32 rxdescuflo;	/* receive descriptor underflows */
    176 	uint32 rxfifooflo;	/* receive fifo overflows */
    177 	uint32 txfifouflo;	/* transmit fifo underflows */
    178 	uint32 runt;		/* runt (too short) frames recv'd from bus */
    179 	uint32 badlen;		/* frame's rxh len does not match its hw tag len */
    180 	uint32 badcksum;	/* frame's hw tag chksum doesn't agree with len value */
    181 	uint32 seqbreak;	/* break in sequence # space from one rx frame to the next */
    182 	uint32 rxfcrc;		/* frame rx header indicates crc error */
    183 	uint32 rxfwoos;		/* frame rx header indicates write out of sync */
    184 	uint32 rxfwft;		/* frame rx header indicates write frame termination */
    185 	uint32 rxfabort;	/* frame rx header indicates frame aborted */
    186 	uint32 woosint;		/* write out of sync interrupt */
    187 	uint32 roosint;		/* read out of sync interrupt */
    188 	uint32 rftermint;	/* read frame terminate interrupt */
    189 	uint32 wftermint;	/* write frame terminate interrupt */
    190 } sdpcmd_cnt_t;
    191 
    192 /*
    193  * Register Access Macros
    194  */
    195 
    196 #define SDIODREV_IS(var, val)	((var) == (val))
    197 #define SDIODREV_GE(var, val)	((var) >= (val))
    198 #define SDIODREV_GT(var, val)	((var) > (val))
    199 #define SDIODREV_LT(var, val)	((var) < (val))
    200 #define SDIODREV_LE(var, val)	((var) <= (val))
    201 
    202 #define SDIODDMAREG32(h, dir, chnl) \
    203 	((dir) == DMA_TX ? \
    204 	 (void *)(uintptr)&((h)->regs->dma.sdiod32.dma32regs[chnl].xmt) : \
    205 	 (void *)(uintptr)&((h)->regs->dma.sdiod32.dma32regs[chnl].rcv))
    206 
    207 #define SDIODDMAREG64(h, dir, chnl) \
    208 	((dir) == DMA_TX ? \
    209 	 (void *)(uintptr)&((h)->regs->dma.sdiod64.dma64regs[chnl].xmt) : \
    210 	 (void *)(uintptr)&((h)->regs->dma.sdiod64.dma64regs[chnl].rcv))
    211 
    212 #define SDIODDMAREG(h, dir, chnl) \
    213 	(SDIODREV_LT((h)->corerev, 1) ? \
    214 	 SDIODDMAREG32((h), (dir), (chnl)) : \
    215 	 SDIODDMAREG64((h), (dir), (chnl)))
    216 
    217 #define PCMDDMAREG(h, dir, chnl) \
    218 	((dir) == DMA_TX ? \
    219 	 (void *)(uintptr)&((h)->regs->dma.pcm32.dmaregs.xmt) : \
    220 	 (void *)(uintptr)&((h)->regs->dma.pcm32.dmaregs.rcv))
    221 
    222 #define SDPCMDMAREG(h, dir, chnl, coreid) \
    223 	((coreid) == SDIOD_CORE_ID ? \
    224 	 SDIODDMAREG(h, dir, chnl) : \
    225 	 PCMDDMAREG(h, dir, chnl))
    226 
    227 #define SDIODFIFOREG(h, corerev) \
    228 	(SDIODREV_LT((corerev), 1) ? \
    229 	 ((dma32diag_t *)(uintptr)&((h)->regs->dma.sdiod32.dmafifo)) : \
    230 	 ((dma32diag_t *)(uintptr)&((h)->regs->dma.sdiod64.dmafifo)))
    231 
    232 #define PCMDFIFOREG(h) \
    233 	((dma32diag_t *)(uintptr)&((h)->regs->dma.pcm32.dmafifo))
    234 
    235 #define SDPCMFIFOREG(h, coreid, corerev) \
    236 	((coreid) == SDIOD_CORE_ID ? \
    237 	 SDIODFIFOREG(h, corerev) : \
    238 	 PCMDFIFOREG(h))
    239 
    240 /*
    241  * Shared structure between dongle and the host
    242  * The structure contains pointers to trap or assert information shared with the host
    243  */
    244 #define SDPCM_SHARED_VERSION       0x0002
    245 #define SDPCM_SHARED_VERSION_MASK  0x00FF
    246 #define SDPCM_SHARED_ASSERT_BUILT  0x0100
    247 #define SDPCM_SHARED_ASSERT        0x0200
    248 #define SDPCM_SHARED_TRAP          0x0400
    249 
    250 typedef struct {
    251 	uint32	flags;
    252 	uint32  trap_addr;
    253 	uint32  assert_exp_addr;
    254 	uint32  assert_file_addr;
    255 	uint32  assert_line;
    256 	uint32	console_addr;		/* Address of hndrte_cons_t */
    257 	uint32  msgtrace_addr;
    258 	uint8   tag[32];
    259 } sdpcm_shared_t;
    260 
    261 extern sdpcm_shared_t sdpcm_shared;
    262 
    263 #endif	/* _bcmsdpcm_h_ */
    264